Invention Grant
- Patent Title: Method and apparatus for efficient scheduling for asymmetrical execution units
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Application No.: US15469460Application Date: 2017-03-24
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Publication No.: US09965285B2Publication Date: 2018-05-08
- Inventor: Nelson N. Chan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F9/38
- IPC: G06F9/38

Abstract:
A method and system performs instruction scheduling in an out-of-order microprocessor pipeline. The method and system selects a first set of instructions to dispatch from a scheduler to an execution module, wherein the execution module comprises two types of execution units. The first type of execution unit executes both a first and a second type of instruction and the second type of execution unit executes only the second type. Next, the method selects a second set of instructions to dispatch, which is a subset of the first set and comprises only instructions of the second type. The method determines a third set of instructions, which comprises instructions not selected as part of the second set. Further, the method dispatches the second set for execution using the second type of execution unit and dispatching the third set for execution using the first type of execution unit.
Public/Granted literature
- US20170199744A1 METHOD AND APPARATUS FOR EFFICIENT SCHEDULING FOR ASYMMETRICAL EXECUTION UNITS Public/Granted day:2017-07-13
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