- Patent Title: Void evaluation apparatus and void evaluation method in the solder
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Application No.: US15034302Application Date: 2014-11-10
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Publication No.: US09965849B2Publication Date: 2018-05-08
- Inventor: Takashi Suzuki , Sueki Baba
- Applicant: OSAKA UNIVERSITY , BEAMSENSE Co., Ltd.
- Applicant Address: JP Osaka JP Osaka
- Assignee: OSAKA UNIVERSITY,BEAMSENSE Co., Ltd.
- Current Assignee: OSAKA UNIVERSITY,BEAMSENSE Co., Ltd.
- Current Assignee Address: JP Osaka JP Osaka
- Agency: Maier & Maier, PLLC
- Priority: JP2013-237024 20131115
- International Application: PCT/JP2014/079717 WO 20141110
- International Announcement: WO2015/072424 WO 20150521
- Main IPC: G06K9/00
- IPC: G06K9/00 ; G06T7/00 ; G01N23/04 ; H05K3/34

Abstract:
A void evaluation apparatus in a solder includes an evaluation function calculation unit for calculating a solder evaluation function by using a pixel value pi contained in the voids that is set to 1 and the pixel value pi not contained in the voids is 0 for each pixel constituting an image in the solder, and by using a weight function w(ri), which is maximum at a solder center (ri=0), and is 0 at a maximum radius (ri=r0) for a distance ri from the solder center. The apparatus further has a void evaluation unit for evaluating that the influence of voids is larger as the evaluation function is relatively larger for the each solder. ∑ i = 1 N w ( r i ) p i ∑ i = 1 N w ( r i ) × 100 i: pixel number (1−N) pi: pixel value (0 or 1) w(ri): weighting function
Public/Granted literature
- US20160267646A1 APPARATUS FOR ASSESSMENT OF VOIDS IN SOLDER AND METHOD FOR ASSESSMENT OF VOIDS IN SOLDER Public/Granted day:2016-09-15
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