Invention Grant
- Patent Title: Memory device
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Application No.: US15459731Application Date: 2017-03-15
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Publication No.: US09966124B2Publication Date: 2018-05-08
- Inventor: Naoki Shimizu
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; G11C11/15

Abstract:
A memory device includes: a memory cell; a data buffer which receives write data; a first latch circuit which latches data stored in the memory cell; a second latch circuit which latches data transferred from the data buffer; a controller which performs a first transfer operation to transfer data from the data buffer to the second latch circuit after a write command is received and then a first period elapses; and a write circuit which performs a write operation to write data of the second latch circuit to the memory cell after the first transfer operation, when data of the first latch circuit is different from the data of the second latch circuit. The controller performs a second transfer operation to transfer data from the second latch circuit to the first latch circuit after the write operation.
Public/Granted literature
- US20180068704A1 MEMORY DEVICE Public/Granted day:2018-03-08
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