Invention Grant
- Patent Title: System for electrical testing of through silicon vias (TSVs)
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Application No.: US15420319Application Date: 2017-01-31
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Publication No.: US09966318B1Publication Date: 2018-05-08
- Inventor: Alberto Pagani
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Crowe & Dunlevy
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L29/86 ; G01R31/28 ; H01L21/66 ; H01L29/861 ; H01L21/768

Abstract:
A substrate includes first and second semiconductor layers doped with opposite conductivity type in contact with each other at a PN junction to form a junction diode. At least one through silicon via structure, formed by a conductive region surrounded laterally by an insulating layer, extends completely through the first semiconductor layer and partially through the second semiconductor layer with a back end embedded in, and in physical and electrical contact with, the second semiconductor layer. A first electrical connection is made to the first through silicon via structure and a second electrical connection is made to the first semiconductor layer. A testing current is applied to and sensed at the first and second electrical connections in order to detect a defect in the at least one through silicon via structure.
Information query
IPC分类: