Invention Grant
- Patent Title: Body tied intrinsic FET
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Application No.: US14963400Application Date: 2015-12-09
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Publication No.: US09966435B2Publication Date: 2018-05-08
- Inventor: Fabio Alessio Marino , Paolo Menegoli
- Applicant: ETA Semiconductor Inc.
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson & Sheridan, L.L.P.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/336 ; H01L29/10 ; H01L29/06 ; H01L29/08 ; H01L29/417 ; H01L29/78

Abstract:
A novel semiconductor transistor is presented. The semiconductor structure has a MOSFET like structure, with the difference that the device channel is formed in an intrinsic region, so as to effectively decrease the impurity and surface scattering phenomena deriving from a high doping profile typical of conventional MOS devices. Due to the presence of the un-doped channel region, the proposed structure greatly reduces Random Doping Fluctuation (RDF) phenomena decreasing the threshold voltage variation between different devices. In order to control the threshold voltage of the device, a heavily doped poly-silicon or metallic gate is used. However, differently from standard CMOS devices, a high work-function metallic material, or a heavily p-doped poly-silicon layer, is used for an n-channel device and a low work-function metallic material, or heavily n-doped poly-silicon layer, is used for a p-channel FET. Doped or insulating regions are used to increase the control on the channel conductivity.
Public/Granted literature
- US20170170276A1 BODY TIED INTRINSIC FET Public/Granted day:2017-06-15
Information query
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