Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. Recesses extend into the conductive levels. The conductive levels have projections above and below the recesses. The projections have outer edges. An outer periphery of an individual conductive level is defined by a straight-line boundary extending from the outer edge of the projection above the recess in the individual conductive level to the outer edge of the projection below the recess in the individual conductive level. A depth of the recess is defined as a horizontal distance from the straight-line boundary to an innermost periphery of the recess. The recesses have depths of at least about 5 nm. Charge-blocking regions extend within the recesses. Charge-storage structures are along the charge-blocking regions. Gate dielectric material is along the charge-storage structures. Channel material is along the gate dielectric material.