Invention Grant
- Patent Title: Capacitance minimization switch
-
Application No.: US14055629Application Date: 2013-10-16
-
Publication No.: US09966911B2Publication Date: 2018-05-08
- Inventor: Tim Morris
- Applicant: Dialog Semiconductor GmbH
- Applicant Address: DE Kirchheim/Teck-Nabern
- Assignee: Dialog Semiconductor GmbH
- Current Assignee: Dialog Semiconductor GmbH
- Current Assignee Address: DE Kirchheim/Teck-Nabern
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman
- Priority: EP13368037 20131007
- Main IPC: H03F3/45
- IPC: H03F3/45 ; H03K17/14 ; H03K17/16 ; H03F1/08

Abstract:
A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the resulting current applied to the input of the transmission gate. A second example uses a current amplifier to detect gate current of the N-channel and P-channel transistors of the transmission gate, and an output current is fed back in phase to the input of the CMOS transmission gate.
Public/Granted literature
- US20150097621A1 Capacitance Minimization Switch Public/Granted day:2015-04-09
Information query