A communication device includes a timing generation circuit generates timing signals at several timing points within one period of a first clock signal. A clock sampling circuit receives the first clock signal and detects a logic level of the first clock signal at each of the timing points. A control circuit calculates a difference between the number of times a first or a second logic level is detected for the first clock signal and outputs a control signal indicating whether a duty ratio of the first clock signal is to be adjusted. A correction circuit that changes at a duty ratio of a second clock signal transmitted to the transmitting device, the duty ratio being set in accordance with the control signal. The duty ratio of the first clock signal is then adjusted by the transmitting device according to the duty ratio of the second clock signal.