An array substrate includes a display region and a non-display region around the display region. The display region comprises a plurality of rows of pixel units arranged sequentially along a first direction and a plurality of gate scanning lines corresponding to the plurality of rows of the pixel units, respectively, and the gate scanning lines extend along a second direction. Cascaded first shift register units are disposed at at least one edge of the non-display region parallel to the second direction, and each of the first shift register units is connected with a corresponding one of the plurality of gate scanning lines; and cascaded second shift register units are disposed at at least one edge of the non-display region parallel to the first direction, and each of the second shift register units is connected with a corresponding one of the plurality of gate scanning line.