Invention Grant
- Patent Title: Stacked RRAM array with integrated transistor selector
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Application No.: US13723164Application Date: 2012-12-20
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Publication No.: US09972386B2Publication Date: 2018-05-15
- Inventor: Pieter Blomme , Dirk Wouters
- Applicant: IMEC
- Applicant Address: BE Leuven
- Assignee: IMEC
- Current Assignee: IMEC
- Current Assignee Address: BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP11195473 20111223
- Main IPC: G11C13/00
- IPC: G11C13/00 ; H01L45/00 ; H01L27/24

Abstract:
The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack.
Public/Granted literature
- US20130161583A1 Stacked RRAM Array With Integrated Transistor Selector Public/Granted day:2013-06-27
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