Invention Grant
- Patent Title: System and method for a field-effect transistor with dual vertical gates
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Application No.: US15485846Application Date: 2017-04-12
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Publication No.: US09972545B2Publication Date: 2018-05-15
- Inventor: Hung-Li Chiang , Chih Chieh Yeh , Cheng-Yi Peng , Tzu-Chiang Chen , Yee-Chia Yeo
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/3065 ; H01L21/265 ; H01L21/285 ; H01L21/324 ; H01L27/092 ; H01L29/423 ; H01L29/06 ; H01L23/535 ; H01L29/66

Abstract:
A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.
Public/Granted literature
- US20170221772A1 System and Method for a Field-Effect Transistor with Dual Vertical Gates Public/Granted day:2017-08-03
Information query
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