Invention Grant
- Patent Title: Integrated magnetic random access memory with logic device having low-k interconnects
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Application No.: US15063544Application Date: 2016-03-08
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Publication No.: US09972775B2Publication Date: 2018-05-15
- Inventor: Danny Pak-Chum Shum , Juan Boon Tan , Yi Jiang , Wanbing Yi , Francis Yong Wee Poh , Hai Cong
- Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Horizon IP PTE Ltd.
- Main IPC: H01L29/82
- IPC: H01L29/82 ; H01L43/12 ; H01L43/08 ; H01L27/22

Abstract:
Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.
Public/Granted literature
- US20160268336A1 INTEGRATED MAGNETIC RANDOM ACCESS MEMORY WITH LOGIC DEVICE HAVING LOW-K INTERCONNECTS Public/Granted day:2016-09-15
Information query
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