A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency fS that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency fS to reduce the sampling frequency fS to a sampling frequency fD=fS/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency fD and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples.