Invention Grant
- Patent Title: Fault tolerant clock network
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Application No.: US14198351Application Date: 2014-03-05
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Publication No.: US09973601B2Publication Date: 2018-05-15
- Inventor: Eric John Spada , Yongbum Kim
- Applicant: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G06F15/16
- IPC: G06F15/16 ; H04L29/06 ; H04J3/06

Abstract:
Fault tolerant and redundant grand master clock scheme may reduce or eliminate precision time transition caused by a network link or device failure. A primary synchronization message may be sent by a primary grandmaster clock and one or more backup synchronization message may be sent by respective backup grandmaster clocks. The primary and backup grandmaster clocks may be concurrently operated. The primary and backup synchronization messages may be sent to an end station over a network. The end station may derive a local clock based on one, some, or all of the received messages. The end station may or may not distinguish between the messages based on the clock source. The end station may validate messages received from a particular clock source.
Public/Granted literature
- US20140281037A1 Fault Tolerant Clock Network Public/Granted day:2014-09-18
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