Invention Grant
- Patent Title: Interconnection substrate and method of inspecting interconnection substrate
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Application No.: US15447374Application Date: 2017-03-02
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Publication No.: US09974162B2Publication Date: 2018-05-15
- Inventor: Tsukasa Obinata , Yusuke Karasawa , Hideyuki Tako , Goshi Imai , Suguru Yamato
- Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
- Applicant Address: JP Nagano
- Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
- Current Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
- Current Assignee Address: JP Nagano
- Agency: IPUSA, PLLC
- Priority: JP2016-051897 20160316
- Main IPC: H05K1/02
- IPC: H05K1/02 ; G06K19/06 ; H05K1/11

Abstract:
An interconnection substrate having a barcode includes a core layer, an interconnection layer over a first surface of the core layer, an insulating layer to cover the interconnection layer, and one or more additional interconnection layers over the insulating layer, wherein the barcode includes cells arranged at spaced intervals, and a cell pattern is made by forming penetrating holes through the core layer in some of the cells but not in remaining ones of the cells, wherein the penetrating holes are filled with resin, and an end face of the resin is exposed on the same side as the first surface such that the interconnection layer is situated in a surrounding area of the end face but not over the end face, and wherein a number of interconnection layers over the end face is smaller than a number of interconnection layers in the surrounding area of the end face.
Public/Granted literature
- US20170273175A1 INTERCONNECTION SUBSTRATE AND METHOD OF INSPECTING INTERCONNECTION SUBSTRATE Public/Granted day:2017-09-21
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