Invention Grant
- Patent Title: 3D memory with error checking and correction function
-
Application No.: US14928317Application Date: 2015-10-30
-
Publication No.: US09984769B2Publication Date: 2018-05-29
- Inventor: Joon-sung Yang , Hyunseung Han
- Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
- Applicant Address: KR Suwon-si
- Assignee: Research & Business Foundation Sungkyunkwan University
- Current Assignee: Research & Business Foundation Sungkyunkwan University
- Current Assignee Address: KR Suwon-si
- Agency: NSIP Law
- Priority: KR10-2014-0149359 20141030; KR10-2015-0125383 20150904
- Main IPC: G11C29/52
- IPC: G11C29/52 ; G11C29/42 ; G11C29/44 ; G11C29/00 ; G06F11/10 ; G11C29/04

Abstract:
An error check and correction method of a 3D memory include a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers.
Public/Granted literature
- US20160124810A1 3D MEMORY WITH ERROR CHECKING AND CORRECTION FUNCTION Public/Granted day:2016-05-05
Information query