Invention Grant
- Patent Title: Method of forming a staircase in a semiconductor device using a linear alignment control feature
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Application No.: US15180902Application Date: 2016-06-13
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Publication No.: US09985046B2Publication Date: 2018-05-29
- Inventor: Zhenyu Lu , Jixin Yu , Koji Miyata , Makoto Yoshida , Johann Alsmeier , Hiro Kinoshita , Daxin Mao
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L27/11582 ; H01L21/66 ; H01L27/11519 ; H01L27/11565 ; H01L27/11556 ; H01L23/528 ; H01L23/522 ; H01L23/544 ; H01L21/768 ; H01L21/311

Abstract:
A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.
Public/Granted literature
- US20170358594A1 METHOD OF FORMING A STAIRCASE IN A SEMICONDUCTOR DEVICE USING A LINEAR ALIGNMNENT CONTROL FEATURE Public/Granted day:2017-12-14
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