Invention Grant
- Patent Title: Single wire system clock signal generation
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Application No.: US15438064Application Date: 2017-02-21
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Publication No.: US09985778B2Publication Date: 2018-05-29
- Inventor: Albert S. Weiner
- Applicant: Atmel Corporation
- Applicant Address: US CA San Jose
- Assignee: Atmel Corporation
- Current Assignee: Atmel Corporation
- Current Assignee Address: US CA San Jose
- Agency: Fish & Richardson P.C.
- Main IPC: H04L7/04
- IPC: H04L7/04 ; H04L7/00 ; H04L12/26

Abstract:
This specification describes an integrated circuit comprising: a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit. The digital system is configured to: receive a data signal from the single wire interface; power the digital system using a power signal from the single wire interface; and perform one or more operations clocked by the clock signal.
Public/Granted literature
- US20170163412A1 SINGLE WIRE SYSTEM CLOCK SIGNAL GENERATION Public/Granted day:2017-06-08
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