Invention Grant
- Patent Title: Binary translation for multi-processor and multi-core platforms
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Application No.: US14129420Application Date: 2013-06-28
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Publication No.: US09990233B2Publication Date: 2018-06-05
- Inventor: Abhik Sarkar , Jiwei Lu , Palanivelrajan Rajan Shanmugavelayutham , Jason M. Agron , Koichi Yamada
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- International Application: PCT/US2013/048563 WO 20130628
- International Announcement: WO2014/209361 WO 20141231
- Main IPC: G06F9/445
- IPC: G06F9/445 ; G06F9/455 ; G06F9/48 ; G06F9/50 ; G06F12/02 ; G06F12/0802

Abstract:
Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.
Public/Granted literature
- US20160188372A1 BINARY TRANSLATION FOR MULTI-PROCESSOR AND MULTI-CORE PLATFORMS Public/Granted day:2016-06-30
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