Invention Grant
- Patent Title: Overlaid erase block mapping
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Application No.: US14518560Application Date: 2014-10-20
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Publication No.: US09990278B2Publication Date: 2018-06-05
- Inventor: Shinsuke Okada , Sunil Atri , Hiroyuki Saito
- Applicant: Cypress Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F12/02
- IPC: G06F12/02

Abstract:
An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB. The second type of EBs store system management information and the third type of EBs store user data. When the flash memory is started up, the overlaid EB mapping scheme scans the corresponding portion to locate the first type of EB, locates the system EBs using the pointers, and locates the data EBs using the system management information.
Public/Granted literature
- US20160110282A1 OVERLAID ERASE BLOCK MAPPING Public/Granted day:2016-04-21
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