Invention Grant
- Patent Title: Cache coherency verification using ordered lists
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Application No.: US15485453Application Date: 2017-04-12
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Publication No.: US09990290B2Publication Date: 2018-06-05
- Inventor: Dean G. Bair , Jonathan T. Hsieh , Matthew G. Pardini , Eugene S. Rotter
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Main IPC: G06F12/0815
- IPC: G06F12/0815 ; G06F12/128 ; G06F12/0808

Abstract:
Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache.
Public/Granted literature
- US20170220468A1 CACHE COHERENCY VERIFICATION USING ORDERED LISTS Public/Granted day:2017-08-03
Information query
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