A ReRAM cell array has having at least one row and one column includes first and second complementary bit lines for each row, a word line, a p-word line, and an n-word line for each column. A ReRAM cell at each row and column of the array includes a first ReRAM device, its first end connected to the first complementary bit line of its row, a p-channel transistor, its source connected to a second end of the first ReRAM device, its drain connected to a switch node, its gate connected to the p-channel word line of its column, a second ReRAM device, its first end connected to the second complementary bit line of its row, an n-channel transistor, its source connected to a second end of the second ReRAM device, its drain connected to the switch node, its gate connected to the n-channel word line of its column.