Invention Grant
- Patent Title: Package method including forming electrical paths through a mold layer
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Application No.: US15480323Application Date: 2017-04-05
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Publication No.: US09991206B1Publication Date: 2018-06-05
- Inventor: Lien-Chia Chang , Chih-Ming Ko , Hung-Hsin Hsu
- Applicant: POWERTECH TECHNOLOGY INC.
- Applicant Address: TW Hsinchu County
- Assignee: POWERTECH TECHNOLOGY INC.
- Current Assignee: POWERTECH TECHNOLOGY INC.
- Current Assignee Address: TW Hsinchu County
- Agent Winston Hsu
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/538 ; H01L21/48 ; H01L21/56 ; H01L23/00 ; H01L23/31 ; H01L21/3105 ; H01L21/288 ; H01L23/498 ; H01L21/027 ; H01L21/3213 ; H01L21/02 ; H01L23/13
Abstract:
A package method includes disposing a chip and a plurality of solder bumps on a substrate by disposing a plurality of chip interfaces and the plurality of solder bumps on a plurality of first interfaces of the substrate respectively; forming a mold layer configured to encapsulate the chip and the plurality of solder bumps; grinding the mold layer to obtain a grinded mold layer and expose a top side of the chip; drilling the grinded mold layer to form a plurality of through holes corresponding to the plurality of solder bumps; and applying a conductive material to fill the plurality of through holes with the conductive material to form a plurality of electrical paths through the grinded mold layer and electrically couple to the plurality of solder bumps.
Information query
IPC分类:
