Invention Grant
- Patent Title: Transistor strain-inducing scheme
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Application No.: US15612137Application Date: 2017-06-02
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Publication No.: US09991364B2Publication Date: 2018-06-05
- Inventor: Tsz-Mei Kwok , Hsueh-Chang Sung , Kun-Mu Li , Chii-Horng Li , Tze-Liang Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/10 ; H01L29/737 ; H01L29/78 ; H01L29/167 ; H01L29/165 ; H01L21/265 ; H01L29/08 ; H01L21/02

Abstract:
A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.
Public/Granted literature
- US20170271478A1 TRANSISTOR STRAIN-INDUCING SCHEME Public/Granted day:2017-09-21
Information query
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