A master-slave flip-flop includes a master latch, a slave latch, a first logic gate and a signal transition detector. The first logic gate is receiving a reference clock and a first control clock, and outputting a first trigger signal to control one of the master latch and the slave latch, which are connected with a logic circuit, to switch to an opaque state or a transparent state, wherein the other one of the master latch and the slave latch is switched to an opaque state or a transparent state according to the reference clock. The above-mentioned master-slave flip-flop can correct sampling when a timing error occurs.