Invention Grant
- Patent Title: Sampling phase-locked loop (PLL)
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Application No.: US15415201Application Date: 2017-01-25
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Publication No.: US09991897B1Publication Date: 2018-06-05
- Inventor: Dongmin Park , Jong Min Park , Yiwu Tang
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson & Sheridan, L.L.P. Qualcomm
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/091 ; H03L7/099 ; H04L7/033

Abstract:
Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch.
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