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    METHOD OF CLEANING A SEMICONDUCTOR WAFER
    2.
    发明申请
    METHOD OF CLEANING A SEMICONDUCTOR WAFER 审中-公开
    清洗半导体波形的方法

    公开(公告)号：WO2007107920A1

    公开(公告)日：2007-09-27

    申请号：PCT/IB2007/050851

    申请日：2007-03-13

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  RINK, Ingrid ,  KNOTTER, Dirk, M. ,  NOIJ, Gilbert, P., A.

    Inventor： RINK, Ingrid ,  KNOTTER, Dirk, M. ,  NOIJ, Gilbert, P., A.

    IPC: H01L21/02 ,  H01L21/306

    CPC classification number: H01L21/02052

    Abstract: The invention provides a method of cleaning the surface (3) of a wafer (1), comprising a hot rinse step in which the wafer (1) is at a temperature that is at least 100C higher than room temperature, the wafer (1) is rotated around an axis perpendicular to the wafer surface (3) and water is dispensed on the wafer surface (3). Thereafter a first drying step is performed in which the wafer (1) is rotated around the axis perpendicular to the wafer surface (3) and in which the humidity of the environment is such that the water on the wafer surface (3) is partially removed while the wafer surface (3) remains covered with a film of water (13). The first drying step is followed by a second drying step, which removes the film of water (13) from the wafer surface (3). The method according to the invention advantageously reduces metal ion contamination on the wafer surface (3).

    Abstract translation: 本发明提供了一种清洁晶片（1）的表面（3）的方法，其包括热冲洗步骤，其中晶片（1）处于比室温高至少100℃的温度，晶片（1） 围绕垂直于晶片表面（3）的轴旋转，并且水分散在晶片表面（3）上。 此后，执行第一干燥步骤，其中晶片（1）围绕垂直于晶片表面（3）的轴线旋转，并且其中环境的湿度使得晶片表面（3）上的水部分地被去除 而晶片表面（3）仍保持用水（13）覆盖。 第一干燥步骤之后是第二干燥步骤，其从晶片表面（3）去除水（13）的膜。 根据本发明的方法有利地减少晶片表面（3）上的金属离子污染。

    DEVICE AND METHOD FOR HOLDING OR TRANSPORTING A SUBSTRATE
    3.
    发明申请
    DEVICE AND METHOD FOR HOLDING OR TRANSPORTING A SUBSTRATE 审中-公开
    用于保持或运输基板的装置和方法

    公开(公告)号：WO2006067730A2

    公开(公告)日：2006-06-29

    申请号：PCT/IB2005/054315

    申请日：2005-12-19

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  KNOTTER, Dirk, M. ,  RASTEGAR, Abbas

    Inventor： KNOTTER, Dirk, M. ,  RASTEGAR, Abbas

    IPC: G03F7/20

    CPC classification number: G03F1/66 ,  G03F7/70741 ,  G03F7/70866 ,  G03F7/70916

    Abstract: Device (1) for holding a substrate, comprising a box (2) and a substrate holder (4). The box (2) is arranged for holding the substrate holder (4), and the substrate holder (4) is arranged for holding the substrate (3). The box (2) comprises a gettering device (5) for gettering an impurity possibly being present within the box (2).

    Abstract translation: 用于保持基板的装置（1），包括盒（2）和基板保持件（4）。 盒子（2）被布置用于保持衬底保持器（4），并且衬底保持器（4）被布置用于保持衬底（3）。 盒（2）包括用于吸收可能存在于盒（2）内的杂质的吸气装置（5）。

    METHOD FOR MANUFACTURING MEMS DEVICES WITH MOVEABLE STRUCTURE
    4.
    发明申请
    METHOD FOR MANUFACTURING MEMS DEVICES WITH MOVEABLE STRUCTURE 审中-公开
    用于制造具有移动结构的MEMS器件的方法

    公开(公告)号：WO2008001252A3

    公开(公告)日：2008-02-21

    申请号：PCT/IB2007052269

    申请日：2007-06-14

    Applicant: NXP BV ,  VAN VELZEN BART ,  VAN BEEK JOZEF T M ,  KNOTTER DIRK M

    Inventor： VAN VELZEN BART ,  VAN BEEK JOZEF T M ,  KNOTTER DIRK M

    IPC: B81B3/00

    CPC classification number: B81C1/00952 ,  B81B3/001 ,  B81C2201/0109

    Abstract: After the release etch of MEMS structures stiction is a well-known problem. Especially for the buried oxide etch on SOI wafers because of the very flat surfaces. Methods to prevent stiction are etching with an etch liquid but the wafers are dried in a CPD tool or alternatively etching with a vapor. However these methods require special equipment and are only effective for the release etch. A simple method for the formation of anti-stiction structures is described in order to prevent direct mechanical contact. The buried oxide is etched in a controlled way and stopped before the buried oxide is totally etched away. The buried oxide residues form anti-stiction structures and prevent direct contact between the resonator and the substrate. For this method no special equipment is required and the process complexity is not increased.

    Abstract translation: MEMS结构静电释放蚀刻之后是众所周知的问题。 特别是对于SOI晶片上的掩埋氧化物蚀刻，因为非常平坦的表面。 防止静电的方法是用蚀刻液蚀刻，但是晶片在CPD工具中干燥，或者替代地用蒸气蚀刻。 然而，这些方法需要特殊的设备，并且仅对释放蚀刻有效。 描述了形成抗静电结构的简单方法，以防止直接的机械接触。 埋入的氧化物以受控的方式蚀刻并在埋入的氧化物被完全蚀刻掉之前停止。 掩埋氧化物残留物形成抗静电结构并防止谐振器和衬底之间的直接接触。 对于这种方法，不需要特殊设备，并且不增加过程复杂性。

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY MEANS OF SUCH A METHOD
    5.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY MEANS OF SUCH A METHOD 审中-公开
    制造这种方法的半导体器件和半导体器件的制造方法

    公开(公告)号：WO2004070834A1

    公开(公告)日：2004-08-19

    申请号：PCT/IB2004/050030

    申请日：2004-01-16

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW ,  LANDER, Robert ,  KNOTTER, Dirk, M.

    Inventor： LANDER, Robert ,  KNOTTER, Dirk, M.

    IPC: H01L21/8238

    CPC classification number: H01L21/823842 ,  Y10S438/976

    Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (1) and a semiconductor body (2) comprising a first (N-MOS)FET (3) with a first channel region (3A) and a first gate electrode (3B) which includes a first conductor and which is separated from the channel region by a dielectric layer (4), and comprising a second (P-MOS)FET (5) with a second channel region (5A) and a second gate electrode (5B) which includes a second conductor that is different from the first conductor and which is separated from the channel region (5A) by a dielectric layer (4), wherein to form the gate electrodes (3B, 5B) a first conductor layer (33) is deposited on the semiconductor body (2) provided with the dielectric layer (4), which layer (33) is subsequently removed outside the first channel region (3A) after which a second conductor layer (55) is deposited on the semiconductor body (2), and wherein before the first conductor layer (33) is deposited, an intermediate layer (6) is deposited on the dielectric layer (4). According to the invention, a material for the intermediate layer (6) is chosen which is selectively etchable with respect to the dielectric layer (4), and before the deposition of the first conductor layer (33) the intermediate layer (6) is removed at the location of the firs channel region (3A), and after the deposition of the first conductor layer (33) and the removal thereof outside the first channel region (3A) and before the deposition of the second conductor layer (55), the intermediate layer (6) is removed at the location of the second channel region (5A). Thus, FETs are obtained in a simple manner and without damage to their gate dielectric. Preferably, a further intermediate layer (8) is deposited on the intermediate layer (6) which is selectively etchable with respect thereto.

    Abstract translation: 本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（1）和半导体本体（2），所述半导体本体（2）包括具有第一沟道区（3A）的第一（N-MOS）FET（3） 栅电极（3B），其包括第一导体，并且通过介电层（4）与沟道区分离，并且包括具有第二沟道区（5A）的第二（P-MOS）FET（5）和第二沟道区 栅电极（5B），其包括与所述第一导体不同的第二导体，并且通过电介质层（4）与所述沟道区（5A）分离，其中，形成所述栅极（3B，5B）的第一导体 层（33）沉积在设置有电介质层（4）的半导体本体（2）上，该层（33）随后在第一沟道区域（3A）之外被移除，之后第二导体层（55）沉积在 半导体本体（2），并且其中在第一导体层（33）沉积之前， ayer（6）沉积在介电层（4）上。 根据本发明，选择用于中间层（6）的材料，其相对于电介质层（4）可选择性地蚀刻，并且在沉积第一导体层（33）之前，中间层（6）被去除 在第一通道区域（3A）的位置处，并且在第一导体层（33）沉积之后并且将其除去在第一沟道区域（3A）之外并且在第二导体层（55）的沉积之前， 在第二通道区域（5A）的位置处去除中间层（6）。 因此，以简单的方式获得FET并且不损坏其栅极电介质。 优选地，在中间层（6）上沉积另外的中间层（8），中间层（6）可相对于其可选择性地蚀刻。

    ETCHING WITH IMPROVED CONTROL OF CRITICAL FEATURE DIMENSIONS AT THE BOTTOM OF THICK LAYERS
    6.
    发明申请
    ETCHING WITH IMPROVED CONTROL OF CRITICAL FEATURE DIMENSIONS AT THE BOTTOM OF THICK LAYERS 审中-公开
    通过改进对厚层底部关键特征尺寸的控制

    公开(公告)号：WO2008084365A2

    公开(公告)日：2008-07-17

    申请号：PCT/IB2007/055353

    申请日：2007-12-31

    Applicant: NXP B.V. ,  KNOTTER, Dirk, M. ,  DEN DEKKER, Arnoldus ,  KOSTER, Ronald ,  VAN SCHAIJK, Robertus, T., F.

    Inventor： KNOTTER, Dirk, M. ,  DEN DEKKER, Arnoldus ,  KOSTER, Ronald ,  VAN SCHAIJK, Robertus, T., F.

    IPC: B81C1/00

    CPC classification number: B81C1/00595 ,  B81C2201/014

    Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometer from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method comprises fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometer, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the crit ical lateral extensio n, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

    Abstract translation: 本发明涉及一种用于蚀刻蚀刻层中的特征的方法，该特征从蚀刻剂的初始接触面到蚀刻层的相对底面具有大于2微米的厚度， 在蚀刻层中的横向特征位置处并且在底面处具有临界横向延伸。 该方法包括在衬底层上的横向特征位置处制造来自掩模层材料的掩模特征，该掩模特征具有临界横向延伸。 蚀刻层被沉积到掩模特征上和衬底层上超过2微米的厚度，由可相对于掩模层材料选择性蚀刻的蚀刻层材料沉积。 然后，使用相对于掩模层材料选择性地移除蚀刻层材料的蚀刻剂，在横向延伸大于临界横向延伸n的第一横向位置蚀刻层中的特征被蚀刻。

    METHOD FOR MANUFACTURING MEMS DEVICES WITH MOVEABLE STRUCTURE
    7.
    发明申请
    METHOD FOR MANUFACTURING MEMS DEVICES WITH MOVEABLE STRUCTURE 审中-公开
    制造具有可移动结构的MEMS器件的方法

    公开(公告)号：WO2008001252A2

    公开(公告)日：2008-01-03

    申请号：PCT/IB2007/052269

    申请日：2007-06-14

    Applicant: NXP B.V. ,  VAN VELZEN, Bart ,  VAN BEEK, Jozef, T., M. ,  KNOTTER, Dirk, M.

    Inventor： VAN VELZEN, Bart ,  VAN BEEK, Jozef, T., M. ,  KNOTTER, Dirk, M.

    IPC: B81C1/00

    CPC classification number: B81C1/00952 ,  B81B3/001 ,  B81C2201/0109

    Abstract: After the release etch of MEMS structures stiction is a well-known problem. Especially for the buried oxide etch on SOI wafers because of the very flat surfaces. Methods to prevent stiction are etching with an etch liquid but the wafers are dried in a CPD tool or alternatively etching with a vapor. However these methods require special equipment and are only effective for the release etch. A simple method for the formation of anti-stiction structures is described in order to prevent direct mechanical contact. The buried oxide is etched in a controlled way and stopped before the buried oxide is totally etched away. The buried oxide residues form anti-stiction structures and prevent direct contact between the resonator and the substrate. For this method no special equipment is required and the process complexity is not increased.

    Abstract translation: 在MEMS结构的释放蚀刻之后，静摩擦是一个众所周知的问题。 特别是对于SOI晶片上的掩埋氧化物蚀刻，因为其表面非常平坦。 防止静摩擦的方法是用蚀刻液进行蚀刻，但晶片在CPD工具中干燥或用蒸气蚀刻。 然而这些方法需要特殊的设备，并且只对释放蚀刻有效。 描述了形成防粘结构的简单方法，以防止直接的机械接触。 掩埋氧化物以受控方式蚀刻，并在掩埋氧化物完全蚀刻掉之前停止。 掩埋的氧化物残余物形成抗静摩擦结构并防止谐振器和衬底之间的直接接触。 对于这种方法，不需要特殊的设备，工艺复杂性也不会增加。

    DEVICE AND METHOD FOR HOLDING A SUBSTRATE
    8.
    发明申请
    DEVICE AND METHOD FOR HOLDING A SUBSTRATE 审中-公开
    用于保持基板的装置和方法

    公开(公告)号：WO2006067730A3

    公开(公告)日：2007-03-15

    申请号：PCT/IB2005054315

    申请日：2005-12-19

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  KNOTTER DIRK M ,  RASTEGAR ABBAS

    Inventor： KNOTTER DIRK M ,  RASTEGAR ABBAS

    IPC: G03F7/20

    CPC classification number: G03F1/66 ,  G03F7/70741 ,  G03F7/70866 ,  G03F7/70916

    Abstract: Device (1) for holding a substrate, comprising a box (2) and a substrate holder (4). The box (2) is arranged for holding the substrate holder (4), and the substrate holder (4) is arranged for holding the substrate (3). The box (2) comprises a gettering device (5) for gettering an impurity possibly being present within the box (2).

    Abstract translation: 用于保持基板的装置（1），包括盒（2）和基板保持件（4）。 盒子（2）被布置用于保持衬底保持器（4），并且衬底保持器（4）被布置用于保持衬底（3）。 盒（2）包括用于吸收可能存在于盒（2）内的杂质的吸气装置（5）。

    ETCHING WITH IMPROVED CONTROL OF CRITICAL FEATURE DIMENSIONS AT THE BOTTOM OF THICK LAYERS
    9.
    发明申请
    ETCHING WITH IMPROVED CONTROL OF CRITICAL FEATURE DIMENSIONS AT THE BOTTOM OF THICK LAYERS 审中-公开
    用改进的关键特征尺寸控制蚀刻在厚层底部

    公开(公告)号：WO2008084365A3

    公开(公告)日：2008-09-04

    申请号：PCT/IB2007055353

    申请日：2007-12-31

    Applicant: NXP BV ,  KNOTTER DIRK M ,  DEN DEKKER ARNOLDUS ,  KOSTER RONALD ,  VAN SCHAIJK ROBERTUS T F

    Inventor： KNOTTER DIRK M ,  DEN DEKKER ARNOLDUS ,  KOSTER RONALD ,  VAN SCHAIJK ROBERTUS T F

    IPC: B81C1/00

    CPC classification number: B81C1/00595 ,  B81C2201/014

    Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometer from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method comprises fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometer, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the crit ical lateral extensio n, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

    Abstract translation: 本发明涉及一种用于蚀刻蚀刻层中的特征的方法，该蚀刻层的特征厚度大于2微米，从蚀刻剂的初始接触面到蚀刻层的相对底面，蚀刻层的横向特征位置 并且在底面具有临界横向延伸。 该方法包括在基底层上的横向特征位置处制造掩模层材料的掩模特征，掩模特征具有临界横向延伸。 蚀刻层在掩模特征和基底层上从相对于掩模层材料可选择性地蚀刻的蚀刻层材料沉积到大于2微米的厚度。 然后，使用相对于掩模层材料选择性去除蚀刻层材料的蚀刻剂，在第一横向位置处蚀刻该特征，其横向延伸大于临界横向延伸n。

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