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公开(公告)号：WO1994001962A1
公开(公告)日：1994-01-20
申请号：PCT/KR1993000055
申请日：1993-07-02
Applicant: KOREA TELECOMMUNICATION AUTHORITY , KWON, Soon, Hong , OH, Yoon, Seok , LEE, Heo, Young , YOON, Jeong, Nam
Inventor： KOREA TELECOMMUNICATION AUTHORITY
IPC: H04M11/00
CPC classification number: H04L41/24 , G06F13/385
Abstract: The Centralized Management System utilizing a Bus Interface Unit comprises a Computer (4z) installing an address Bus (4a), data Bus (4b), and control Bus (4c), a First-Level Station (4Q1) communicating with the Computer (4z) as the First-Level Station (4Q1) is connected to the buses (4a, 4b, 4c) of the Computer (4z), a plurality of second-level stations (4Q2, 4Q3, ..., 4QM) communicating with the First-Level Station (4Q1) as the second-level stations (4Q2, 4Q3, ..., 4QM) are connected to the First-Level Station through a Multipoint Bus (4r). Therefore, the Centralized Management System is capable of communicating the Computer with the First-Level Station through a Dual Port RAM (Random Access Memory), intercommunicating a plurality of Second-Level Stations through a Multipoint Interface and Multipoint Bus, and controlling and managing several thousands of Terminals (for example, Public Telephones).
Abstract translation: 使用总线接口单元的集中管理系统包括安装地址总线（4a），数据总线（4b）和控制总线（4c）的计算机（4z），与计算机（4z）通信的一级站（4Q1） ）将第一级站（4Q1）连接到计算机（4z）的总线（4a，4b，4c），多个第二级站（4Q2,4Q3，...，4QM）与 第一级站（4Q1）作为二级站（4Q2,4Q3，...，4QM）通过多点总线（4r）连接到一级站。 因此，集中管理系统能够通过双端口RAM（随机存取存储器）将计算机与一级站通信，通过多点接口和多点总线将多个二级站相互通信，并且控制和管理几个 数千个终端（例如，公用电话）。
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公开(公告)号：WO1994017519A1
公开(公告)日：1994-08-04
申请号：PCT/KR1994000007
申请日：1994-01-28
Applicant: KOREA TELECOMMUNICATION AUTHORITY , LEE, Chong, Rak
Inventor： KOREA TELECOMMUNICATION AUTHORITY
IPC: G10L05/06
Abstract: The present invention relates to a speech synthesis and recognition system that reduces the amount of memory capacity for storing standard speech information, and improves the synthesized speech quality and the rate of speech recognition. The speech synthesis and recognition system has a memory with the stored demiphoneme data bisected with respect to a center of phoneme, and produces a synthesis speech signal by decoding demiphoneme data stored in the memory and concatenating the decoded demiphoneme data while generating a character train data for word, phrase, clause corresponding to speech signal by comparing the demiphoneme data stored in the memory with the speech signal.
Abstract translation: 本发明涉及一种减少用于存储标准语音信息的存储容量的语音合成和识别系统，并且提高了合成语音质量和语音识别率。 语音合成和识别系统具有存储的相对于音素中心二维的存储的虹吸数据的存储器，并且通过解码存储在存储器中的demiphoneme数据并连接解码的虹吸数据来产生合成语音信号，同时产生用于 通过将存储在存储器中的虹吸数据与语音信号进行比较来对应于语音信号的单词，短语，子句。
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公开(公告)号：WO1994000828A1
公开(公告)日：1994-01-06
申请号：PCT/KR1993000050
申请日：1993-06-18
Applicant: KOREA TELECOMMUNICATION AUTHORITY , KWON, Soon, Hong , KIM, Eun, Ho , JIN, Byung, Wook , JOO, Woon, Yong
Inventor： KOREA TELECOMMUNICATION AUTHORITY
IPC: G07D03/04
CPC classification number: G07F5/24
Abstract: A coin treatment apparatus, for selecting the inserted coins by each currency unit, transferring them to a receiving space of a predetermined position, and discharging various coins stored in the receiving space into a coin receiving box (3) which is another receiving space, is constructed.
Abstract translation: 一种硬币处理装置，用于通过每个货币单元选择插入的硬币，将其转移到预定位置的接收空间，并将存储在接收空间中的各种硬币放入作为另一个接收空间的硬币接收盒（3）中， 建。
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公开(公告)号：WO1994000947A1
公开(公告)日：1994-01-06
申请号：PCT/KR1993000051
申请日：1993-06-18
Applicant: KOREA TELECOMMUNICATION AUTHORITY , KIM, Eun, Ho , JIN, Byung, Wook , JOO, Woon, Yong , YOON, Jeong, Nam
Inventor： KOREA TELECOMMUNICATION AUTHORITY
IPC: H04M17/00
Abstract: A coin/credit operated public telephone is capable of making local, toll, and international calls using coins, credit card, or IC card and also of making a voice announcement regarding its operation method to the caller through a handset (1). Moreover, it provides graphic/character information through the LCD (10) and can transmit fault status that has been detected as a result of a highly reliable self-diagnosis carried out by receiving control signals from a remotely located central management system.
Abstract translation: 硬币/信用公用电话机能够通过手机（1）向硬币，信用卡或IC卡进行本地，长途和国际电话，并且通过手机（1）向呼叫者发送关于其操作方法的语音通知。 此外，它通过LCD（10）提供图形/字符信息，并且可以通过从远程位置的中央管理系统接收控制信号来发送作为通过高度可靠的自诊断的结果而检测到的故障状态。
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5.发明申请System of providing agency service for customer management and method thereof 审中-公开为客户管理提供代理服务的制度及其方法公开(公告)号：US20020065670A1
公开(公告)日：2002-05-30
申请号：US09752981
申请日：2000-12-29
Applicant: Korea Telecommunication Authority
Inventor： Dong Kwon Cho , Byeong Wook Lee
IPC: G06F017/60
CPC classification number: G06Q30/02 , H04M3/5183
Abstract: The present invention relates to a system of providing an agency service for customer management using a CTI (Computer Telephony Integration) technique and a method thereof. The system comprises a system of providing an agency service for customer management having a switchboard, a CTI server and a subscriber management module, and a call center of an enterprise mutually connected to the system. By means of such construction, the enterprise using the system can easily ascertain customer information previously constructed in the system to rapidly and effectively carry out counsel with a subscriber. The system of providing an agency service for customer management using a CTI technique can reduce costs of investment and maintenance required for expensive equipments, associated experts and the like.
Abstract translation: 本发明涉及使用CTI（计算机电话集成）技术及其方法为客户管理提供代理服务的系统。 该系统包括提供具有交换机，CTI服务器和订户管理模块的客户管理的代理服务以及与系统相互连接的企业的呼叫中心的系统。 通过这种建设，使用该系统的企业可以很容易地确定系统中先前构建的客户信息，以便用户快速有效地进行咨询。 使用CTI技术为客户管理提供代理服务的系统可以降低昂贵设备，相关专家等所需的投资和维护成本。
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Patent Agency Ranking
公开(公告)号：DE4222844A1
公开(公告)日：1993-05-06
申请号：DE4222844
申请日：1992-07-11
Inventor： VERZICHT DES ERFINDERS AUF NENNUNG
Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.
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公开(公告)号：FR2714240B1
公开(公告)日：1998-09-04
申请号：FR9415427
申请日：1994-12-21
Inventor： LEE SANG HOON , KO JUNG HOON , LEE TAE HEE , SHIM CHANG SUP
Abstract: Ce dispositif comprend des moyens de sélection 2:1 (8) pour sélectionner l'un de deux signaux d'entrée présentant des écarts temporels, des moyens (28) de production de signaux de sélection, des moyens (9) de production de signaux de commande pour le démultiplexage des données qui ont été sélectionnées, des moyens (10) de démultiplexage pour démultiplexer sous la forme de données à faible vitesse, les données qui ont été sélectionnées, des moyens (12) de multiplexage pour réaliser la synchronisation sur un signal synchrone de trame de référence et un signal d'horloge de référence et multiplexer les données délivrées par les moyens (10) de démultiplexage, et des moyens (11) de production de signaux de référence. Application notamment aux systèmes de transfert numérique de données.
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公开(公告)号：DE3939635C2
公开(公告)日：1993-09-23
申请号：DE3939635
申请日：1989-11-30
Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, DAEJEON, KR , KOREA TELECOMMUNICATION AUTHORITY, SEOUL/SOUL, KR
IPC: H01L29/812 , H01L21/285 , H01L21/338 , H01L29/417 , H01L29/78
Abstract: The invention provides the method of manufacturing a self-aligned GaAs MESFET wherein the Si thin film formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) and the Si3N4 film formed by PCVD (Photo Chemical Vapor Deposition) onto the GaAs substrate are used as the capping film in the activation process, and then the self-aligned MESFET with the T type gate is manufactured through the selective chemical vapor deposition of the tungsten onto the Si thin film. As a result, the gap between the gate electrode and the n+ layer can be adjusted itself.
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公开(公告)号：DE4222846A1
公开(公告)日：1993-05-06
申请号：DE4222846
申请日：1992-07-11
Inventor： VERZICHT DES ERFINDERS AUF NENNUNG
Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.
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公开(公告)号：DE3941252C2
公开(公告)日：1992-08-20
申请号：DE3941252
申请日：1989-12-14
Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, DAEJEON, KR , KOREA TELECOMMUNICATION AUTHORITY, SEOUL/SOUL, KR
Abstract: A reframe circuit in a synchronous multiplexing device comprising a frame synchronizing pattern detection circuit, a frame pattern bit error detection circuit responsive to a serial data stream from the frame synchronizing pattern detection circuit, an in-frame/out-of-frame state discrimination circuit responsive to the output signal from the frame pattern bit error detection circuit and the output signal from the synchronizing pattern detection circuit, a counter phase synchronizing circuit responsive to the output signal from the in-frame/out-of-frame state discrimination circuit, the output signal from the frame synchronization pattern detection circuit and a reference phase signal, and a counter and timing generation circuit responsive to the operating mode control signal from the counter phase synchronizing circuit.
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