公开(公告)号：WO1997040500A1

公开(公告)日：1997-10-30

申请号：PCT/JP1997001267

申请日：1997-04-11

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  NAKANE, Joji ,  MORIWAKI, Nobuyuki

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: G11C11/22

CPC classification number: H01L27/11502 ,  G11C11/22

Abstract: A nonvolatile ferroelectric semiconductor memory to which rewrite can be performed stably without losing data of a low logical voltage in memory cells. In the memory, for example, diodes (1 and 2) are connected to cell plate lines (39 and 40) as shown in the figure. When rewrite is performed, therefore, the transient phenomenon that the voltage at the cell plate line (39) temporarily changes to a negative overvoltage (for example, below -1 V), causing the data to be lost, is prevented.

Abstract translation: 可以在不损失存储单元中的低逻辑电压的数据的情况下稳定地执行重写的非易失性铁电半导体存储器。 在存储器中，例如，如图所示，二极管（1和2）连接到单元板线（39和40）。 因此，当进行重写时，防止了电池板线（39）处的电压暂时变为负过电压（例如低于-1V）的瞬态现象，导致数据丢失。

公开(公告)号：WO1996002067A1

公开(公告)日：1996-01-25

申请号：PCT/US1995008575

申请日：1995-07-10

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A. ,  SCOTT, Michael, C. ,  CUCHIARO, Joseph, D.

IPC: H01L21/3205

CPC classification number: H01L27/11502 ,  C04B35/4682 ,  C04B35/6264 ,  C04B2235/3213 ,  C04B2235/3224 ,  C04B2235/3227 ,  C04B2235/3229 ,  C04B2235/3243 ,  C04B2235/3268 ,  C04B2235/441 ,  C04B2235/449 ,  C04B2235/72 ,  C23C16/4412 ,  C23C16/448 ,  C23C16/4486 ,  C23C16/45561 ,  C23C16/4558 ,  C23C16/46 ,  C23C16/482 ,  C23C16/52 ,  C23C18/1216 ,  C23C18/1275 ,  C23C18/1295 ,  C23C18/14 ,  C30B7/00 ,  C30B29/68 ,  H01C7/1013 ,  H01L21/314 ,  H01L21/31691 ,  H01L27/10805 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60

Abstract: A xylene exchange (P44) is performed on a stock solution of BST of greater than 99.999 % purity dissolved in methoxyethanol, and a carboxylate of a dopant metal, such as magnesium 2-ethylhexanoate is added to form a precursor. The precursor is spun (P45) on a first electrode (14), dried (P46) at 400 DEG C for 2 minutes, then annealed (P47) at 750 DEG C to 800 DEG C for about an hour to form a layer (15) of accurately doped BST. A second electrode (16) is deposited (P48), patterned (P49), and annealed (P50) at between 750 DEG C to 800 DEG C for about 30 minutes. Excellent leakage current results if the dopant is magnesium of about 5 % molarity. For other dopants, such as Mg, Nb, Y, Bi, and Sn the preferred dopant range is 0.2 % to 0.3 % molarity. The magnesium-doped material is used as a buffer layer (25, 27) between the electrodes (24, 28) and BST dielectric (26) of an undoped BST capacitor (20).

Abstract translation: 对溶解在甲氧基乙醇中的纯度大于99.999％的BST的原液进行二甲苯交换（P44），加入2-乙基己酸镁等掺杂剂金属的羧酸盐，形成前体。 将前体在第一电极（14）上旋转（P45），在400℃下干燥（P46）2分钟，然后在750℃至800℃下退火（P47）约1小时以形成层（15 ）精确掺杂的BST。 在750℃至800℃下沉积第二电极（P48），图案化（P49）和退火（P50）约30分钟。 如果掺杂剂为约5％摩尔浓度的镁，则会产生优异的漏电流。 对于其他掺杂剂如Mg，Nb，Y，Bi和Sn，优选的掺杂剂范围为0.2％至0.3％摩尔浓度。 镁掺杂材料用作未掺杂的BST电容器（20）的电极（24,28）和BST电介质（26）之间的缓冲层（25,27）。

公开(公告)号：WO1996001493A1

公开(公告)日：1996-01-18

申请号：PCT/US1995008296

申请日：1995-06-30

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A. ,  SCOTT, Michael, C.

IPC: H01L21/3205

CPC classification number: H01L27/11502 ,  C23C18/1216 ,  C23C18/1295 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60

Abstract: A method for fabricating an integrated circuit capacitor (10, 20, 30) having a dielectric layer (15, 26, 37) comprising BST with excess A-site and B-site materials such as barium and titanium added. An organometallic or metallic soap precursor solution is prepared (P42) comprising a stock solution of BST of greater than 99.999 % purity blended with excess A-site and B-site materials such as barium and titanium such that the barium is in the range of 0.01-100 mol %, and such that the titanium is in the range of 0.01-100 mol %. A xylene exchange (P44) is then performed to adjust the viscosity of the solution for spin-on application to a substrate. The precursor solution is spun on a first electrode (P45), dried (P46) at 400 DEG C for 2 to 10 minutes, then annealed (P47) at 650 DEG C to 800 DEG C for about an hour to form a layer of BST with excess titanium. A second electrode is deposited (P48), patterned (P49), and annealed at between 650 DEG C to 800 DEG C for about 30 minutes. The resultant capacitor (10, 20, 30) exhibits an enlarged dielectric constant with little change in leakage current.

Abstract translation: 一种用于制造集成电路电容器（10,20,30）的方法，该集成电路电容器具有包含BST的介电层（15,26,37），该BST具有过量的A位和B位的材料如钡和钛。 制备有机金属或金属皂前体溶液（P42），其包含与超过99.99％纯度的BST的储备溶液混合的过量A位和B位物质如钡和钛，使得钡在0.01 -100摩尔％，并且使得钛在0.01-100摩尔％的范围内。 然后进行二甲苯交换（P44）以调节溶液的粘度，以便旋涂到基底上。 将前体溶液在第一电极（P45）上旋转，在400℃下干燥（P46）2至10分钟，然后在650℃至800℃退火（P47）约1小时以形成BST层 与多余的钛。 沉积第二电极（P48），图案化（P49），并在650℃至800℃下退火约30分钟。 所得到的电容器（10,20,30）的介电常数增大，漏电流几乎没有变化。

公开(公告)号：WO1997049119A1

公开(公告)日：1997-12-24

申请号：PCT/JP1997001750

申请日：1997-05-26

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  MATSUSHITA ELECTRONICS CORPORATION ,  YAMADA, Yuka ,  YOSHIDA, Takehito ,  TAKEYAMA, Shigeru ,  MATSUDA, Yuji ,  MUTOH, Katsuhiko

Inventor： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  MATSUSHITA ELECTRONICS CORPORATION

IPC: H01L21/203

CPC classification number: H01L33/26 ,  H01L31/1804 ,  H01L33/0054 ,  H01L33/18 ,  Y02E10/547 ,  Y02P70/521 ,  Y10T428/25 ,  Y10T428/258

Abstract: A photoelectronic material is composed of a homogeneous medium which can be controlled in electrical property and ultrafine semiconductor particles which have a mean particle diameter of not larger than 100 nm and scattered in the medium and an element to which the material is applied. In a method for manufacturing the photoelectronic material, a layer in which the ultrafine semiconductor particles are scattered in the medium is formed on a substrate by respectively irradiating a first target which is set in a reaction chamber maintained in a low-pressure rare gas atmosphere and composed of a semiconductor material and a second target which is set in the chamber and composed of a medium material which can be controlled in electrical property with laser beams and collecting ultrafine semiconductor particles having a mean particle diameter of not larger than 100 nm on the substrate by condensing and growing the semiconductor material ablated from the first target and, at the same time, collecting the medium material on the substrate by condensing and growing the material ablated from the second target.

Abstract translation: 光电子材料由平均粒径不大于100nm的电性质的均匀介质和分散在介质中的元素和施加材料的元素构成。 在制造光电子材料的方法中，通过分别照射设置在保持在低压稀有气体气氛中的反应室中的第一靶，在基板上形成其中超介质半导体颗粒在介质中散射的层，以及 由半导体材料和第二靶组成，其设置在腔室中并且由可以用激光束控制在电性质中的介质材料构成，并且在基板上收集平均粒径不大于100nm的超微粒半导体颗粒 通过冷凝和生长从第一靶材烧蚀的半导体材料，并且同时通过冷凝和生长从第二靶材烧蚀的材料来收集介质材料。

公开(公告)号：WO1997036300A1

公开(公告)日：1997-10-02

申请号：PCT/JP1997000893

申请日：1997-03-19

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  HIRANO, Hiroshige

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: G11C11/22

CPC classification number: H01L27/11502 ,  G11C11/22

Abstract: A ferroelectric storage device which can further reduce the fluctuation of the reference potential in a reference memory cell system. The storage device is provided with a reference potential generating circuit which generates a reference potential by averaging potentials read out from two ferroelectric capacitors CD00 and CD20 for reference memory cells storing high-level data and two ferroelectric capacitors CD10 and CD30 for reference memory cells storing low-level data.

Abstract translation: 一种可以进一步减小参考存储单元系统中的参考电位波动的铁电存储装置。 存储装置设置有参考电位产生电路，其通过平均从两个强电介质电容器CD00和CD20读出的电位来产生参考电位，用于存储高电平数据的参考存储单元和两个用于存储低电平的参考存储单元的铁电电容器CD10和CD30 级数据。

公开(公告)号：WO1997013360A1

公开(公告)日：1997-04-10

申请号：PCT/JP1996002875

申请日：1996-10-02

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  TERAOKA, Koji ,  EMOTO, Fumiaki ,  KAWASHIMA, Hideya

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: H04N05/66

CPC classification number: H04N5/66 ,  H04N3/233 ,  H04N7/0122

Abstract: A method for driving a matrix video display by which a distortion-free picture is displayed according to video signals having an arbitrary aspect ratio. On the screen (7) of a first aspect ratio of the display, a first video display area (8) of a second aspect ratio where a picture is displayed according to video signals having the second aspect ratio and a second video display area (9) which is the other area than the first area (8) of the first aspect ratio are provided. The second area (9) is used for black display. Such timing of the vertical and horizontal clock signals N, Q that the aspect ratio of the first area (8) is equal to that of video signals H is adopted. The vertical scanning of the display (4) is such that the vertical scanning frequency of the second area (9) is higher than that of the first area (8). The horizontal scanning of the device (4) is such that the horizontal scanning frequency of the second area (9) is higher than that of the first area (8).

Abstract translation: 一种用于驱动矩阵视频显示的方法，通过该矩阵视频显示根据具有任意宽高比的视频信号显示无失真图像。 在显示器的第一宽高比的屏幕（7）上，根据具有第二宽高比的视频信号和第二视频显示区域（9），显示第二宽高比的第一视频显示区域（8），其中显示图像 ）是第一宽高比的第一区域（8）的另一区域。 第二区（9）用于黑色显示。 采用垂直和水平时钟信号N，Q的定时，第一区域（8）的宽高比等于视频信号H的宽高比。 显示器（4）的垂直扫描使得第二区域（9）的垂直扫描频率高于第一区域（8）的垂直扫描频率。 装置（4）的水平扫描使得第二区域（9）的水平扫描频率高于第一区域（8）的水平扫描频率。

公开(公告)号：WO1997007546A1

公开(公告)日：1997-02-27

申请号：PCT/US1996013310

申请日：1996-08-19

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos

IPC: H01L29/51

CPC classification number: C23C18/14 ,  C04B35/62227 ,  C23C16/448 ,  C23C16/45561 ,  C23C18/1216 ,  C23C18/1225 ,  C23C18/1295 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01L21/314 ,  H01L21/31691 ,  H01L27/10805 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L29/78391

Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxyde superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.

Abstract translation: MIS器件（20）包括半导体衬底（22），氮化硅缓冲层（24），铁电金属氧化物超晶格材料（26）和贵金属顶电极（28）。 层状超晶格材料（26）优选为钽酸锶锶，铌酸铋锶或钽酸铋铌钽酸锶。 根据优选的方法构造器件，其包括在沉积层状超晶格材料之前在半导体衬底上形成氮化硅。 层状超晶格材料优选使用液体聚氧化烷基化的金属有机前体沉积，其在加热前体溶液时自发产生层状超晶格。 在前体液体的干燥期间的紫外线曝光赋予最终晶体C轴取向，并且导致改善的薄膜电性能。

公开(公告)号：WO1997007408A1

公开(公告)日：1997-02-27

申请号：PCT/JP1996002295

申请日：1996-08-14

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  HIRANO, Hiroshige ,  ASARI, Kouji ,  SUMI, Tatsumi

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: G01R19/00

CPC classification number: H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

Abstract: A voltage detecting circuit is provided with a first MOS transistor the gate and drain of which are connected to a first node, a second MOS transistor the gate and drain of which are respectively connected to the first node and a third node, a first resistor connected between the first node and a second node, a second resistor connected between the second node and a ground voltage terminal, a first NOT circuit the input terminal of which is connected to the second node, the output terminal of which is a fourth node and which is connected between the third node and the ground voltage terminal, and a second NOT circuit the input terminal of which is connected to the fourth node, and the output terminal of which is a fifth node. The circuit stably detects a voltage without consuming much electric power.

Abstract translation: 电压检测电路设置有第一MOS晶体管，栅极和漏极连接到第一节点，第二MOS晶体管的栅极和漏极分别连接到第一节点和第三节点，第一电阻器连接 在所述第一节点和第二节点之间，连接在所述第二节点和地电压端子之间的第二电阻器，其输入端连接到所述第二节点的第一NOT电路，其输出端子是第四节点， 连接在第三节点和地电压端子之间，以及第二非电路，其输入端连接到第四节点，其输出端子是第五节点。 电路稳定地检测电压而不消耗大量电力。

公开(公告)号：WO1995025340A1

公开(公告)日：1995-09-21

申请号：PCT/US1995003254

申请日：1995-03-16

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A. ,  SCOTT, Michael, C. ,  UEDA, Toshiyuki

IPC: H01L21/3205

CPC classification number: C23C18/1225 ,  C23C18/1216 ,  H01L21/31691 ,  H01L28/55

Abstract: A silicone nitride barrier layer (12) is deposited on a gallium arsenide substrate (11) to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer (14) is deposited on the barrier layer. A first electrode (16) comprising an adhesion layer (18) and a second layer (20) is formed on the stress reduction layer. An essentially anhydrous alkoxycarboxylate liquid precursor is prepared, just before use a solvent exchange step is performed, then the precursor is spun on the first electrode, dried at 400 DEG C, and annealed at between 600 DEG C and 850 DEG C to form a BST capacitor dielectric (22). A second electrode (24) is deposited on the dielectric and annealed.

Abstract translation: 将氮化硅阻挡层（12）沉积在砷化镓衬底（11）上，以防止随后的加热步骤中衬底的蒸发。 二氧化硅应力减少层（14）沉积在阻挡层上。 在应力降低层上形成包括粘合层（18）和第二层（20）的第一电极（16）。 制备基本上无水的烷氧基羧酸盐液体前体，刚好在使用前进行溶剂交换步骤，然后将前体在第一电极上纺丝，在400℃下干燥，并在600℃和850℃之间退火以形成BST 电容电介质（22）。 第二电极（24）沉积在电介质上并退火。

公开(公告)号：WO1997040528A1

公开(公告)日：1997-10-30

申请号：PCT/JP1997001346

申请日：1997-04-18

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  HIRANO, Hiroshige ,  HONDA, Toshiyuki

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: H01L21/3205

CPC classification number: H01L28/55 ,  H01L28/60

Abstract: In a ferroelectric storage device, the influences of lower electrodes (111a and 111b) constituting ferroelectric capacitors (110a1-110a3 and 110b1-110b3) and the thermal stresses of the electrodes (111a and 111b) on a ferroelectric layer (113) formed on the electrodes (111a and 111b) can be relieved and, as a result, the disconnection of wires (106a1, 106a2, etc.) connected to the elect rodes (111a and 111b) due to the thermal stresses of the electrodes (111a and 111b) or the characteristic fluctuation or variation of the ferroelectric capacitors (110a1-110a3 and 110b1-110b3) due to the thermal stresses of the electrodes (111a and 111b) applied to the ferroelectric layer (113) are suppressed. The electrodes (111a and 111b) are bent at a plurality of points so that the electrodes can have zigzag planar shapes and divided into pluralities of wiring sections (111a1 and 111a2 and 111b1 and 111b2).

Abstract translation: 在铁电存储装置中，形成铁电电容器（110a1-110a3和110b1-110b3）的下电极（111a和111b）以及电极（111a和111b）对形成在铁电电容器上的铁电层（113）的热应力的影响 可以减轻电极（111a和111b），并且因此，由于电极（111a和111b）的热应力而连接到电极（111a和111b）的电线（106a1,106a2等）的断开， 或者由于施加到铁电体层（113）的电极（111a，111b）的热应力引起的铁电电容器（110a1-110a3,110b1-110b3）的特性波动或变化被抑制。 电极（111a和111b）在多个点处弯曲，使得电极可以具有锯齿形平面形状并分成多个布线部分（111a1和111a2和111b1和111b2）。