公开(公告)号：WO2009094674A2

公开(公告)日：2009-07-30

申请号：PCT/US2009/035251

申请日：2009-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BLANER, Bartholomew ,  BROWN, Mary, D. ,  BURKY, William, E. ,  VENTON, Todd, A.

Inventor： BLANER, Bartholomew ,  BROWN, Mary, D. ,  BURKY, William, E. ,  VENTON, Todd, A.

IPC: G06F1/04

CPC classification number: G06F1/3203 ,  G06F1/10 ,  G06F1/3237 ,  Y02D10/128

Abstract: A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register (112) in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers (116) in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs (202) used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register (112) in the second pipeline stage.

Abstract translation: 一种用于在多级流水线设计中实现数字逻辑电路的推测时钟门控的方法包括在第一流水线级n中产生输入到第二流水线级n + 1中的第一寄存器（112）的有效控制信号， 指示何时由第二流水线级n + 1执行操作的有效控制信号; 以及在所述第一流水线级中产生用于在第二流水线级中向多个附加寄存器（116）门控时钟信号的推测有效控制信号，其中所述推测有效控制信号仅使用 用于产生有效控制信号的控制输入（202）的总数，并且其中在第二流水线级中将时钟信号直接发送到第一流水线级的第一寄存器（112）。

公开(公告)号：WO2009094674A3

公开(公告)日：2010-01-21

申请号：PCT/US2009035251

申请日：2009-02-26

Applicant: IBM ,  BLANER BARTHOLOMEW ,  BROWN MARY D ,  BURKY WILLIAM E ,  VENTON TODD A

Inventor： BLANER BARTHOLOMEW ,  BROWN MARY D ,  BURKY WILLIAM E ,  VENTON TODD A

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/10 ,  G06F1/3237 ,  Y02D10/128

Abstract: A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register (112) in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers (116) in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs (202) used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register (112) in the second pipeline stage.

Abstract translation: 一种用于在多级流水线设计中实现数字逻辑电路的推测时钟门控的方法包括在第一流水线级n中产生输入到第二流水线级n + 1中的第一寄存器（112）的有效控制信号， 指示何时由第二流水线级n + 1执行操作的有效控制信号; 以及在所述第一流水线级中产生用于在第二流水线级中向多个附加寄存器（116）门控时钟信号的推测有效控制信号，其中所述推测有效控制信号仅使用 用于产生有效控制信号的控制输入（202）的总数，并且其中在第二流水线级中将时钟信号直接发送到第一流水线级的第一寄存器（112）。