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    Chip-Scale Sensorchip-Packung
    1.
    发明专利
    Chip-Scale Sensorchip-Packung 未知

    公开(公告)号：DE202015102619U1

    公开(公告)日：2015-06-23

    申请号：DE202015102619

    申请日：2015-05-21

    Applicant: XINTEC INC

    IPC: H01L23/50 ,  B81B7/02 ,  H01L23/28

    Abstract: Chip-Scale Sensorchip-Packung, aufweisend: einen Sensorchip, mit einer ersten Oberfläche und einer gegenüberliegenden ersten Unterfläche, aufweisend: eine Sensorvorrichtung, die neben der ersten Oberfläche gebildet ist, und eine Vielzahl von leitfähigen Pads, die neben der ersten Oberfläche und angrenzend zu der Sensorvorrichtung gebildet sind; eine Vielzahl von ersten Durchgangslöchern, die an der ersten Unterfläche gebildet sind, wobei jedes der ersten Durchgangslöcher dessen korrespondierende leitfähige Pad freilegt; eine Vielzahl von leitfähigen Strukturen, die an der ersten Unterfläche gebildet sind; und eine Umverteilungsschicht, welche die erste Unterfläche und die ersten Durchgangslöcher überlagert, um eine Verbindung zu jedem der leitfähigen Pads und jeder der leitfähigen Strukturen herzustellen; eine Abstandsschicht, welche die Sensorvorrichtung umgibt, die am Sensorchip gebildet ist, wobei die Abstandsschicht eine zweite Oberfläche und eine zweite gegenüberliegende Unterfläche und eine Öffnung durch die zweite Oberfläche und die zweite Unterfläche aufweist, und die Innenwand der Öffnung in eine vorbestimmten Abstand d (d > 0) zu der Sensorvorrichtung verbleibt; und eine erste Klebeschicht im Sandwich zwischen der zweiten Unterfläche der Abstandsschicht und der ersten Oberfläche des Sensorchips.

    Chip package and method for fabricating the same
    5.
    发明公开
    Chip package and method for fabricating the same 审中-公开
    Chipbaugruppe und Herstellungsverfahrendafür

    公开(公告)号：EP2357665A2

    公开(公告)日：2011-08-17

    申请号：EP11151515.1

    申请日：2011-01-20

    Applicant: Xintec Inc.

    Inventor： Lou, Bai-Yao ,  Liu, Tsang-Yu ,  Yeou, Long-Sheng

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L27/14618 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: An embodiment of the invention provides a chip package, which includes a substrate (100) having an upper surface and a lower surface, a chip (102) disposed in or on the substrate, a pad (104) disposed in or on the substrate and electrically connected to the chip, a hole extending from the lower surface toward the upper surface, exposing the pad, wherein a lower opening of the hole near the lower surface has a width that is shorter than that of an upper opening of the hole near the upper surface, an insulating layer (114a) located overlying a sidewall of the hole, and a conducting layer (116) located overlying the insulating layer and electrically connected to the pad.

    Abstract translation: 本发明的一个实施例提供一种芯片封装，其包括具有上表面和下表面的衬底（100），设置在衬底中或衬底上的芯片（102），设置在衬底中或衬底上的焊盘（104） 电连接到芯片，从下表面向上表面延伸的孔，暴露焊盘，其中靠近下表面的孔的下开口的宽度比孔附近的孔的上开口的宽度短 上表面，位于所述孔的侧壁上方的绝缘层（114a）以及位于所述绝缘层上并电连接到所述焊盘的导电层（116）。

    Passive device formed on glass substrate and fabrication method thereof
    8.
    发明公开
    Passive device formed on glass substrate and fabrication method thereof 审中-公开
    Passives Bauelement auf Glassubstrat und Herstellungsverfahrendafür

    公开(公告)号：EP2287892A2

    公开(公告)日：2011-02-23

    申请号：EP10172894.7

    申请日：2010-08-16

    Applicant: Xintec Inc.

    Inventor： Ni, Ching-Yu

    IPC: H01L21/02 ,  H01F5/00

    CPC classification number: H01L28/60 ,  H01F17/0013 ,  H01F41/041 ,  H01L27/12 ,  H01L28/10

    Abstract: An electronic device and fabrication method thereof are provided. The electronic device contains a glass substrate (100), a patterned semiconductor substrate (108), having at least one opening (122,124), disposed on the glass substrate and at least one passive component (200A,200B) having a first conductive layer (104a,104b) and a second conductive layer (112a-c), wherein the first conductive layer is disposed between the patterned semiconductor substrate and the glass substrate.

    Abstract translation: 提供了一种电子设备及其制造方法。 该电子设备包括玻璃基板（100），具有设置在玻璃基板上的至少一个开口（122,124）的图案化半导体基板（108）和至少一个具有第一导电层的无源部件（200A，200B） 104a，104b）和第二导电层（112a-c），其中第一导电层设置在图案化的半导体衬底和玻璃衬底之间。

    Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region
    9.
    发明授权
    Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region 有权

    公开(公告)号：US12272712B2

    公开(公告)日：2025-04-08

    申请号：US17744664

    申请日：2022-05-14

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu Liu ,  Chaung-Lin Lai ,  Shu-Ming Chang

    IPC: H01L21/48 ,  H01L27/146

    Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

    Chip package and method for forming the same
    10.
    发明授权
    Chip package and method for forming the same 有权

    公开(公告)号：US12237354B2

    公开(公告)日：2025-02-25

    申请号：US17683917

    申请日：2022-03-01

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Chaung-Lin Lai

    IPC: H01L27/146

    Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

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