公开(公告)号：KR1020030039843A

公开(公告)日：2003-05-22

申请号：KR1020010071194

申请日：2001-11-15

Applicant: 정정화

Inventor： 정정화 ,  윤상훈 ,  백정기

IPC: H03M13/41

CPC classification number: H03M13/4169 ,  H03M13/1145 ,  H03M13/6505

Abstract: PURPOSE: A pipeline Viterbi decoder structure design provided with an effective memory structure by improving a trace back is provided to reduce the overall size thereof without requiring TB block by processing at each stage, thereby eliminating the memory required for the TB. CONSTITUTION: A pipeline Viterbi decoder structure design provided with an effective memory structure by using a trace back forecast includes a BM module provided with a plurality of BMs for receiving a received sequence, a plurality of registers, a PM, a MIN_PM and a TB memory for outputting a decoded sequence.

Abstract translation: 目的：提供一种通过改进追溯来提供有效存储器结构的管线维特比解码器结构设计，以减少其整体尺寸，而不需要在每个阶段处理TB块，从而消除TB所需的存储器。 构成：通过使用回溯预测提供有效存储器结构的管线维特比解码器结构设计包括具有多个BM的BM模块，用于接收接收到的序列，多个寄存器，PM，MIN_PM和TB存储器 用于输出解码的序列。