公开(公告)号：WO2015020788A1

公开(公告)日：2015-02-12

申请号：PCT/US2014/047576

申请日：2014-07-22

Applicant: APPLE INC.

Inventor： PAASKE, Timothy R. ,  WARREN, David S. ,  SMITH, Michael J. ,  ROSS, Diarmuid P. ,  MAO, Weihua

IPC: G06F21/72 ,  G06F21/85 ,  G06F21/60 ,  G06F21/87

CPC classification number: G06F12/1408 ,  G06F21/602 ,  G06F21/72 ,  G06F21/85 ,  G06F21/87 ,  G09C1/00 ,  H04L9/12 ,  H04L2209/12

Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.

Abstract translation: 在一个实施例中，外围接口控制器可以包括内联密码引擎，其可以对通过外围接口发送的数据进行加密，并解密从外围接口接收的数据。 加密可能对连接到正在接收/提供数据的外设接口的设备是透明的。 在一个实施例中，外围接口控制器包括在芯片上的系统（SOC）中，该系统还包括被配置为耦合到存储器的存储器控​​制器。 存储器可以以片上芯片或封装的封装形式安装在SOC上。 未加密的数据可以存储在存储器中以供SOC的其他部分使用（例如处理器，片上外设等）。 用于加密/解密数据的密钥可能保留在SOC内。

公开(公告)号：WO2013032751A1

公开(公告)日：2013-03-07

申请号：PCT/US2012/051526

申请日：2012-08-20

Applicant: APPLE INC. ,  WARREN, David S.

Inventor： WARREN, David S.

IPC: G06F1/04 ,  H03M1/36

CPC classification number: G06F13/1689 ,  G06F13/385 ,  G06F13/4045 ,  H04L1/1874

Abstract: An apparatus includes a first unit and a second functional units operating in a master-slave configuration. The first and second functional units operate as a master and slave, respectively. The first functional unit conveys clock and framing signals to the second functional unit. The second functional unit includes a buffer and a multiplexer having inputs coupled to the buffer. Digital audio data may be prefetched into the buffer. When a controller of the second functional unit detects assertion of the framing signal, it may cause a change of state to a selection signal provided to the multiplexer. Responsive thereto, the multiplexer selects an input coupled to receive, from the buffer, a next frame of data to be transmitted. A first bit of the frame is transmitted to the first functional unit on the same clock cycle in which assertion of the framing signal was detected.

Abstract translation: 一种装置包括以主从配置工作的第一单元和第二功能单元。 第一和第二功能单元分别作为主机和从机操作。 第一功能单元向第二功能单元传送时钟和帧信号。 第二功能单元包括缓冲器和具有耦合到缓冲器的输入的多路复用器。 数字音频数据可以被预取到缓冲器中。 当第二功能单元的控制器检测到成帧信号的断言时，可能导致状态改变为提供给多路复用器的选择信号。 响应于此，复用器选择耦合以从缓冲器接收要发送的下一个数据帧的输入。 该帧的第一位在检测到成帧信号的断言的相同时钟周期被发送到第一功能单元。

公开(公告)号：WO2015041773A2

公开(公告)日：2015-03-26

申请号：PCT/US2014/050744

申请日：2014-08-12

Applicant: APPLE INC.

Inventor： WARREN, David S. ,  LEVIT, Inna ,  PAASKE, Timothy R.

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/3296 ,  G06F1/06 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/325 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract translation: 公开了可以允许管理计算系统的功率的装置和方法的实施例。 该装置可以包括时钟发生电路，总线接口单元和控制电路。 时钟发生电路可以被配置为产生多个时钟信号。 每个时钟信号可以提供与耦合到通信总线的设备内的不同功能块的定时参考。 总线接口单元可以被配置为经由通信总线从设备接收消息。 消息可以包括延迟值和激活低功率模式的请求。 控制电路可以被配置为取决于等待时间值和多个阈值的多个时钟信号中的一个或多个。