公开(公告)号：JPH08279747A

公开(公告)日：1996-10-22

申请号：JP8448196

申请日：1996-03-14

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： MARUKO BURUTSUIO

IPC: H03K19/0175 ,  H03D13/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To speedily match a clock signal with the clock of a data signal by allowing a main PLL of the clock extracting circuit to control VCO by continuously controlling the phase and allowing an auxiliary PLL to lock a main loop by oscillating the VCO at a frequency close to an operating frequency. SOLUTION: The extracting circuit for the clock from the high-speed data stream has twin-loop PLL structure. The main loop consisting of a phase detector DFS, a driving current generator PC1, a loop filter FI, and VCO locks the phase of a clock signal which is generated by the VCO and present on a wiring to data arriving at the wiring 1. The subordinate loop consisting of a threshold comparator CS, a driving current generator PC2, a filter FI, and VCO locks the main loop by oscillating the VCO at the frequency close to a desired frequency. When the VCO oscillates a frequency greatly different from the optimum frequency and the wiring frequency is too low, the frequency detector DFR outputs an error pulse to the wire 4 and when the frequency of the wiring 2 is too high, an error pulse is generated to a wiring 5 to control the oscillation frequency of the VCO, thereby approximating its frequency to the desired frequency.

公开(公告)号：JPH09153889A

公开(公告)日：1997-06-10

申请号：JP31569496

申请日：1996-11-13

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： MARUKO BURUTSUIO ,  PAORO PEREGURIINO

IPC: H04L7/08 ,  H03M9/00 ,  H04J3/04 ,  H04L12/56 ,  H04Q3/00 ,  H04Q11/04 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To provide a serialigation-parallelization converting circuit for a high speed digital signal. SOLUTION: This serialization-parallelization converting circuit includes a transmitter(TX) and a receiver(RX) on one integrated circuit chip(IC). The transmitter(TX) parallel-serial-converts a data stream, inserts a period word in a prescribed period within this serial scream and line-codes this serial stream. The receiver(RX) draws a clock signal synchronized with the data stream from the serial stream of coded data, decodes data and serial-parallel-converts this decoded signal. These transmitter(TX) and receiver(RX) are constituted to execute the parallel operation of 4 or 8-bit.