公开(公告)号：WO1997032252A1

公开(公告)日：1997-09-04

申请号：PCT/US1997003000

申请日：1997-02-25

Applicant: DATA GENERAL CORPORATION

Inventor： DATA GENERAL CORPORATION ,  ESPY, James, W. ,  BLEIWEISS, Scott, J. ,  HAWKINS, Thomas, B. ,  BROWN, Jeffrey, A.

IPC: G06F11/30

CPC classification number: G06F11/3058 ,  G06F11/3034 ,  G06F11/3041 ,  G06F11/3051 ,  G06F11/3055 ,  G06F13/409 ,  H04L5/20

Abstract: A dynamically upgradeable disk array chassis (10), a method for dynamically upgrading a data storage system, diplexed computer communications and a diplexer (50) wherein the diplexer (50) and the diplexed communications may be used in the dynamically upgradeable disk array chassis (10). The dynamically upgradeable disk array chassis (10) includes a serial bus (22) having a first bus for passing data in one direction and a second bus (24) for passing data in the opposite direction. A shunt (40) connects the first (22) and second (24) buses in a normal state. The shunt (40) has a switched state in which each of the first and second buses is coupled to a separate output from the chassis. The chassis (10) includes an environmental monitor (30) connected to a communication path (42). Upon connecting a new disk array chassis to an active disk array chassis, the environmental monitor (30) communicates through the communication path (42) before switching the shunt (40) to connect the serial bus with the serial bus of the new disk array chassis. The disk array chassis (10) may include a diplexer (50) for connecting the communication path (42) to the separate outputs of the shunt (40) and for combining the communicaton path signals with the serial path signals in one direction and for separating these signals in the other direction. The diplexer (50) may include an adder for adding the signals from the communication path with those on the serial path and a subtractor for subtracting signals of one path from the other. The environmental monitor path communications and the serial bus communications can take place over a single twinax cable (18). One signal is differentially coupled onto a first pair of conductors. A second signal is common mode coupled onto the first pair of conductors. In the opposite direction on the twinax cable (18), different signals are also differentially coupled and common mode coupled to the return pair of conductors.

Abstract translation: 动态可升级的磁盘阵列机箱（10），用于动态升级数据存储系统，双工计算机通信和双工器（50）的方法，其中所述双工器（50）和所述双工通信可以用在所述可动态可升级的磁盘阵列机箱（ 10）。 动态可升级的磁盘阵列机箱（10）包括具有用于在一个方向上传送数据的第一总线的串行总线（22）和用于相反方向传递数据的第二总线（24）。 分流器（40）以正常状态连接第一（22）和第二（24）总线。 分流器（40）具有开关状态，其中第一和第二总线中的每一个耦合到与机架的单独输出。 底盘（10）包括连接到通信路径（42）的环境监视器（30）。 在将新的磁盘阵列机箱连接到活动磁盘阵列机箱之前，环境监视器（30）在切换分流器（40）之前通过通信路径（42）进行通信，以将串行总线与新磁盘阵列机箱的串行总线连接 。 磁盘阵列机箱（10）可以包括用于将通信路径（42）连接到分流器（40）的分离输出的双工器（50），并且用于将通信路径信号与串行路径信号组合在一个方向上并用于分离 这些信号在另一个方向。 双工器（50）可以包括用于将来自通信路径的信号与串行路径上的信号相加的加法器，以及用于从另一路径减去一个路径的信号的减法器。 环境监控通道和串行总线通信可以通过单个双芯电缆（18）进行。 一个信号差分耦合到第一对导体上。 第二信号是耦合到第一对导体上的共模。 在Twinax电缆（18）的相反方向上，不同的信号也差分耦合，并且共模耦合到导体的返回对。

公开(公告)号：WO1998037491A1

公开(公告)日：1998-08-27

申请号：PCT/US1997015747

申请日：1997-10-08

Applicant: DATA GENERAL CORPORATION

Inventor： DATA GENERAL CORPORATION ,  PETERSON, Gary, S.

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F2211/104

Abstract: In an array of data storage disks, a data validation system for data arranged in corresponding sectors of a sector group that includes a parity sector. Each user data sector in a sector group is assigned at least two of a plurality of validation fields for placement of a validation stamp. No two data sectors are assigned to identically corresponding sets of validation fields. In the parity sector, there is a parity entry in each of the validation fields created by combining all of the validation stamps in the corresponding validation field throughout the sector group. The validation fields are used to detect partially completed writes into the array of data storage disks.

Abstract translation: 在一组数据存储磁盘中，用于数据验证系统，用于布置在包括奇偶校验扇区的扇区组的相应扇区中的数据。 扇区组中的每个用户数据扇区被分配用于放置验证戳的多个验证字段中的至少两个。 没有两个数据扇区被分配给相同对应的验证字段集合。 在奇偶校验部分中，通过将整个扇区组中的相应验证字段中的所有验证戳合并而创建的每个验证字段中都有一个奇偶校验条目。 验证字段用于检测部分完成的写入数据存储磁盘阵列。

公开(公告)号：WO1998021660A1

公开(公告)日：1998-05-22

申请号：PCT/US1997017432

申请日：1997-09-29

Applicant: DATA GENERAL CORPORATION

Inventor： DATA GENERAL CORPORATION ,  ESPY, James, W. ,  BLEIWEISS, Scott, J. ,  HAWKINS, Thomas, B. ,  BROWN, Jeffrey, A.

IPC: G06F13/00

CPC classification number: G06F11/3055 ,  G06F11/3034 ,  G06F11/3051 ,  G06F13/409 ,  H04L5/20

Abstract: A dynamically upgradeable disk array chassis (10) and method for dynamically upgrading a data storage system. The dynamically upgradeable disk array chassis (10) includes a serial bus having a first bus (22) and a second bus (24). A shunt (40) connects the first bus (22) and the second bus (24) in a normal state, and has a switched state in which the first and second buses are coupled to separate outputs from the chassis. The chassis (10) includes an environmental monitor (30) which, upon connecting a new disk array chassis, communicates through a communication path (42) before switching the shunt (40) to connect the serial bus with a serial bus of a new disk array chassis. A diplexer (50) may be used for connecting the communication path (42) to the separate outputs of the shunt (40) and for combining and separating the communication path and serial path signals.

Abstract translation: 一种用于动态升级数据存储系统的动态可升级磁盘阵列机箱（10）和方法。 动态可升级的磁盘阵列机箱（10）包括具有第一总线（22）和第二总线（24）的串行总线。 分流器（40）在正常状态下连接第一总线（22）和第二总线（24），并且具有开关状态，其中第一和第二总线耦合到从机箱分离的输出。 底盘（10）包括环境监视器（30），在连接新的盘阵列机箱之前，在切换分流器（40）之前通过通信路径（42）进行通信，以将串行总线与新磁盘的串行总线连接 阵列机箱。 双工器（50）可以用于将通信路径（42）连接到分流器（40）的单独输出端，并用于组合和分离通信路径和串行路径信号。

公开(公告)号：WO1997007457A1

公开(公告)日：1997-02-27

申请号：PCT/US1996013742

申请日：1996-08-14

Applicant: DATA GENERAL CORPORATION ,  BAXTER, William, F. ,  WEILER, Pat, J. ,  COX, Joseph ,  GELINAS, Robert, G. ,  GILLOTT, Barry, E. ,  GUYER, James, M. ,  HEYDA, Andrea ,  HUCK, Dan, R. ,  HUNT, Michael, F. ,  KEATING, David, L. ,  KIMMELL, Jeff, S. ,  PIKE, Rob, J. ,  RADOGNA, Tom, V. ,  ROUX, Phil, J. ,  SHERMAN, Art, A. ,  SPORTER, Michael ,  TRUEBENBACH, Liz, M. ,  TUCKER, Doug, J. ,  VALENTINE, Rob, P. ,  YEUNG, Simon, N.

Inventor： DATA GENERAL CORPORATION

IPC: G06F11/00

CPC classification number: G06F11/2289 ,  G06F11/22 ,  G06F11/267 ,  G06F12/0813 ,  G06F13/36 ,  G06F2212/2542

Abstract: A high availability computer system and methodology including a backplane, having at least one backplane communication bus (208a-d) and a diagnostic bus (206), a plurality of motherboards (202a-h), each interfacing to the diagnostic bus (206). Each motherboard (202a-h) also includes a memory system (252) including main memory distributed among the plurality of motherboards (202a-h), at least one daughterboard (250a-b) and a scan chain that electrically interconnects functionalities mounted on each motherboard (202a-h) and daughterboard (250a-b). The system including instructions and criteria to automatically test the functionalities and electrical connections, using the scan chain, to determine the presence of faulted components and to functionally remove the faulted components from the computer system.

Abstract translation: 一种高可用性计算机系统和方法，包括具有至少一个背板通信总线（208a-d）和诊断总线（206）的背板，每个与诊断总线（206）接口的多个主板（202a-h） 。 每个主板（202a-h）还包括存储器系统（252），其包括分布在多个主板（202a-h）中的主存储器，至少一个子板（250a-b）和扫描链，其将安装在每个主板 主板（202a-h）和子板（250a-b）。 该系统包括使用扫描链来自动测试功能和电连接的指令和标准，以确定故障组件的存在并从计算机系统中功能地去除故障组件。

公开(公告)号：WO1998021657A1

公开(公告)日：1998-05-22

申请号：PCT/US1997018522

申请日：1997-10-08

Applicant: DATA GENERAL CORPORATION

Inventor： DATA GENERAL CORPORATION ,  ESPY, James, W. ,  BLEIWESS, Scott ,  SOLOMON, Robert, C. ,  BAILEY, Brian, K. ,  EVERDELL, Peter

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F11/201 ,  G06F11/2089

Abstract: A fail-over switch (100, 102) for use in a data storage system that connects each of a plurality of data storage devices (112) to each of two communication paths (126, 128). The switch (100, 102) may route requests to either of the two communication paths (126, 128). Switching may be accomplished by two switches (100, 102) connected to each other and each in connection with one of the two communication paths (126, 128). With one data storage controller (90) in communication with the data storage devices (112) over a first path (126) and a second data storage controller (92) in communication with the data storage devices (112) over a second path (128), the fail-over switch (100, 102) may be used upon detection of a malfunction on one path to switch a controller into connection with the remaining operable path so as to share that path with the other controller.

Abstract translation: 一种用于将多个数据存储设备（112）中的每一个连接到两个通信路径（126,128）中的每一个的数据存储系统中的故障切换开关（100,102）。 交换机（100,102）可以将请求路由到两个通信路径（126,128）中的任何一个。 可以通过彼此连接并且与两个通信路径（126,128）中的一个连接的两个交换机（100,102）来实现切换。 通过在第二路径（128）上与数据存储设备（112）通信的第一路径（126）和第二数据存储控制器（92）与数据存储设备（112）通信的一个数据存储控制器（90） ），故障切换开关（100,102）可以在检测到一个路径上的故障时使用，以将控制器切换成与剩余可操作路径连接，从而与另一控制器共享该路径。

公开(公告)号：WO1998021656A1

公开(公告)日：1998-05-22

申请号：PCT/US1997018523

申请日：1997-10-08

Applicant: DATA GENERAL CORPORATION

Inventor： DATA GENERAL CORPORATION ,  SOLOMON, Robert, C. ,  BAILEY, Brian, K. ,  YATES, Robert ,  EVERDELL, Peter ,  REEVES, Elizabeth, H.

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F2211/1054

Abstract: A high performance data path for performing XOR on the fly. A first memory is connected to a first bus and a second memory is connected to a second bus selectively coupled to the first bus. Logic for performing an XOR can be switched into connection with the first and second bus for XORing data in a buffer with the data passed from one of the memories to the other memory. The result is replaced into the buffer to permit successive XORing. When reading from an interrelated group of disks such as a RAID 3 group, the data path permits an N-1 and go mode in which a read does not wait for data from the last disk to retrieve its data sector. If the last disk contains data (as opposed to parity) the data is obtained from the XORed data in the XOR buffer of the high performance data path. For writing data, the XOR on the fly generates the parity sector for writing at the completion of a write to an interrelated group of disks.

Abstract translation: 用于执行XOR的高性能数据路径。 第一存储器连接到第一总线，第二存储器连接到选择性地耦合到第一总线的第二总线。 用于执行XOR的逻辑可以切换成与第一和第二总线连接，用于将数据从一个存储器传递到另一个存储器的缓冲器中的数据进行异或运算。 结果被替换为缓冲区以允许连续的异或。 当从相互关联的诸如RAID 3组的磁盘组读取数据路径时，数据路径允许N-1和去模式，其中读取不等待来自最后一个磁盘的数据来检索其数据扇区。 如果最后一个磁盘包含数据（与奇偶校验相反），则从高性能数据路径的XOR缓冲区中的异或数据获取数据。 对于写入数据，XOR在写入到相互关联的一组磁盘完成时，将产生用于写入的奇偶校验扇区。

公开(公告)号：WO1987005431A1

公开(公告)日：1987-09-11

申请号：PCT/US1987000420

申请日：1987-02-26

Applicant: DATA GENERAL CORPORATION

Inventor： DATA GENERAL CORPORATION ,  MURDOCH, Robert

IPC: G11C07/00

CPC classification number: G11C15/04

Abstract: A content addressable memory cell (10) which employs a structure which utilizes a single transistor (56, 76) to discharge the hit line (20) and is driven by a self-blocking driver (12) which glitchlessly changes state without the use of virtual ground nodes. Also disclosed is an alternative content addressable memory (14) cell which can be written into two distinct fashions, one of which permits the content of the cell to be changed without requiring the entire data word with which the cell is associated to be rewritten.

Abstract translation: 一种内容可寻址存储器单元（10），其采用利用单个晶体管（56,76）来排出所述命中线（20）并由无阻碍地改变状态的自阻挡驱动器（12）驱动的结构，而不使用 虚拟地面节点。 还公开了一种可替代的内容可寻址存储器（14）单元，其可以被写入两个不同的时尚，其中之一允许改变单元的内容，而不需要重写与单元相关联的整个数据字。