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    Improvements in or relating to electronic data processing machines
    1.
    发明专利
    Improvements in or relating to electronic data processing machines 未知

    公开(公告)号：GB1108800A

    公开(公告)日：1968-04-03

    申请号：GB1360665

    申请日：1965-03-31

    Applicant: IBM

    Inventor： AMDAHL GENE MYRON ,  JOHNSON JACOB RAYMOND ,  ROOD JOHN WILLIS ,  CRANEVALE RICHARD JOSEPH ,  UPDIKE BRUCE MARTIN ,  VILLANTE ANTHONY EUGENE ,  BLAAUW GERRIT ANNE ,  WEBER HELMUT ,  CALINGAERT PETER ,  CASE RICHARD PAUL ,  BOEHM ELAINE MARIE ,  HANE WILLIAM PORTER ,  JR CHARLES BERTRAM PERKINS ,  COLLINS ARTHUR FREDERICK ,  GREENE JACK ELLIS ,  MAGDALL ALBERT ALLAN

    IPC: G06F3/00 ,  G06F3/06 ,  G06F3/12 ,  G06F7/38 ,  G06F7/50 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/302 ,  G06F9/32 ,  G06F9/46 ,  G06F11/16 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/22 ,  G06F13/26 ,  G06F13/38 ,  G06F15/78 ,  G06F17/21

    Abstract: 1,108,800. Electric digital calculators and data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. 31 March, 1965 [6 April, 1964], No. 13606/65. Headings G4A and G4C. In a data processor, variable-format macroinstructions read from a main memory into selected registers control accessing of a microprogramme read-only store. Data representations-The machine can handle: (a) Fixed-point numbers which are signed binary numbers of one of two lengths. (b) Floating-point numbers (signed) consisting of a " fraction " field of single or double precision length containing binary-coded hexadecimal digits, the fraction field being considered multiplied by 16 raised to the power of a number given in a 7-bit " characteristic " field. (c) Decimal numbers containing a variable number of binary-coded decimal digits, the code 1101 being used to indicate " minus " and the other unused four-bit codes to indicate " plus." Two BCD digits occupy an 8-bit byte in the so-called packed format, or the byte contains one digit plus zone bits in the unpacked (or zoned) format. (d) Logical information in various length fields. Macro-instruction format.-(Figs. 21-25, not shown). Each macro-instruction contains besides an operation code, either (a) the addresses of two operands (RR), or (b) the address of one operand, and two fields which when added give the address of a register containing a number to be added to another field in the instruction to give a second operand address (RX), or (c) two operand addresses and a field to be added to the contents of a register specified by another field in the instruction to give a third operand address (RS), or (d) fields specifying the lengths of two operands, the addresses of two registers and two numbers which when added to the contents of the registers respectively give the addresses of the left-most bytes of the two operands (SS), or (e) one operand (directly) and the address of a register the contents of which are to be added to those of another field in the instruction to get the address of a single-byte second operand (SI). The formats used for different types of operations are as follows: floating-point (RR, RX), fixed-point (RR, RX, RS), decimal (SS), logical (RR, RX, RS, RI, SS). In all macro-instructions, the first two bits of the operation code portion specify the instruction format and length. Programme status words (Fig. 27a, not shown).-One of these words partially controls machine operation at any one time. When operation is interrupted (e.g. for I/O servicing), the current programme status word (PSW) is stored and another is introduced. The PSW has fields to specify: (a) which possible sources of interruption are permitted to cause interruption, (b) storage protection key, (c) whether detection of a machine malfunction is to result in interruption, and execution of diagnostic procedures, (d) whether the CPU is running or waiting, (e) whether the CPU is executing a problem programme or a monitor programme, (f) cause of interruption, (g) length of last instruction executed, (h) condition code, (i) which of four events are to result in interruption, the events being fixed-point overflow, decimal overflow, exponent overflow, and " significance " (i.e. the occurrence of an allzero fraction in the result of a floating-point addition or subtraction), (j) address of next macro-instruction. Possible sources of interruption.-(a) Request for I/O operation. (b) Programme interruption due to programme error. (c) Monitor call. (d) External, e.g. when a timer value is decremented beyond zero, when an operator presses a button or when an external unit (e.g. another CPU) signals on any one of six lines provided. (e) Detection of machine malfunction. A predetermined priority order is provided for simultaneous interrupt attempts. If the storage protection feature is not provided in the computer, detection of a non-zero protection key in the PSW causes an immediate interruption. Manual controls.-These include: (a) A rate switch determining whether the machine will operate continuously on being started, or perfoim one macro-instruction and then stop until restarted. (b) Address keys to address a storage location within a storage area selected by a storage selection switch. (c) Data keys for specifying data to be stored in an addressed location, (d) A button to cause display of information in an addressed location. (e) Address compare switches to set an address on recognition of which the CPU will stop. Read-only storage.-(Figs. 4am, 45a-45c, 46a-46d, not shown).-Two decoders select a driver transistor by signals applied to the base and emitter terminals respectively to read out two words in a capacitive read-only store to sense-amplifiers, the outputs of half the amplifiers being stored in latches under control of a further address bit. By this scheme the number of drivers is halved by doubling the number of amplifiers. Alternatively, each driver may read out four words, the number of amplifiers being twice as large again, and so on. Arithmetic and logic unit and checking. (Figs. 35a-35i, not shown).-The ALU can perform addition or subtraction (binary or decimal) or AND, OR, EXCLUSIVE-OR functions, depending on control signals. Operations are done on the normal and inverted forms of the operands and the results compared to give an error indication if inconsistent. Multiplication.-Binary multiplication is done utilizing tables in which the multiplier is stored in both single and doubled form. Decimal multiplication is done by an algorithm involving successive subtractions followed by multiplicand end digit testing operations and shift of multiplier. Division.-Binary division is by repeated addition or subtraction operations of the divisor to/from the dividend, each followed by shift of the dividend, whether the addition or subtraction operation is used at any time depending on the sign of the result of the last operation. Decimal division is done by repeated subtraction. Other features.-The Specification describes a complete micro-programme-controlled computer in considerable detail, including for instance a complete dictionary of micro-instruction words, and micro-programmes for representative macroinstructions. Also described are details of control of input/output (I/O) operations, editing, branching, memory protection and other features, which are, however, the subject of separate patents.

    4.
    发明专利
    未知

    公开(公告)号：DE1095026B

    公开(公告)日：1960-12-15

    申请号：DEI0012345

    申请日：1956-10-19

    Applicant: IBM DEUTSCHLAND

    Inventor： ROCHESTER NATHANIEL ,  JOHNSON JACOB RAYMOND ,  AMDAHL GENE MYRON ,  MUTTER WALTER EDWARD

    IPC: G06K9/46

    Abstract: 845,548. Character recognition. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 19,1956 [Oct. 20, 1955], No. 31860/56. Class 106 (1). The numerals or characters of an intelligence pattern are interpreted by sensing means detecting the presence of intersections and bounded regions in each of the entities and differentiating by the types of intersections and bounded regions therein. The scanning device need not be light and the representations may be magnetic, sonic, chemical or electrostatic. The recognition of numerals is described, using the detection of triple intersections by a central vertical line, upper and lower inlets to left and right, long vertical and black lines and the presence of lakes (Fig. 13, not shown). The area containing the numeral is scanned by a light spot bit by bit in vertical sweeps giving black or white (1, 0) responses, and a memory device stores the respective signals allowing coded signal representations of the combinations to be recorded and interpreted as the presence or absence of the various characteristics of the numerals. The provision of a Shape Rules Circuit and a memory trigger storage enables a decoder of Christmas tree shape to detect the numeral being scanned and operate the appropriate punch or output. The Shape Rules circuit modifies the coded numbers in a marking register and the shape memory triggers are turned on or the contents of the marking register modified by the logical coincidence of certain events involving the presence of white or black, the contents of the register and the state of the temporary triggers. The flow diagram, Fig. 1, shows scan, control and recognition circuits. The light spot from C.R.T. scanner 70 is reflected by the symbols on a document 74 to give a signal at photo-tubes 76 which is fed to a Black-White circuit 80 comprising anplifiers and limiters giving black and white signals at leads B, B, respectively. The line scanning is vertically upwards in thirty-two steps, only sixteen of which are used for recognition purposes, and the beam is unblanked for only a short period at each elemental area. The horizontal frame scan is from left to right and a complete absence of black in any vertical scan indicates end of character. The recognition circuits comprise shape rule circuit 96 and storage means comprising a marking register 97 and memory triggers 98, the latter storing the findings of circuits 96. The marking register has 16 storage positions, one for each area of vertical scan, each assigned an arbitrary coded number. White is coded -, black is coded 1, white following black horizontally is coded 2, black following a white coded 2 is coded 5, a white area between a lower black intercept and a middle black intercept is coded 3, and a white area between a middle black and an upper black is coded 4, Figs. 14 and 16. Coded 3 and 4 at the end of character indicate lower and upper right inlet respectively. Each coded number is fed from the shape rules circuit 96, via digit encode circuit 120 into the marking register 97. A series of coded 0's actuates the reset and endof-character circuit 132, the signal being fed to " O.K. to Punch " lead 136 and the decoder circuit 100. The character recognised proceeds to control the punch 102. The circuits of cathode followers, multi-grid switches, inverters, " And " and " 0 + " circuits, limiters, amplifiers, photo-multipliers, triggers, multivibrators, counters, peakers, core and relay drivers deflection units and core-shifting registers are described (Figs. 19-74, not shown). The document is carried on a standard electric typewriter which is stationary for a period of 32 vertical sweeps before spacing in the usual way, although in a modification the light spot sweeps vertically over a continuously-moving document. The travel of the carriage is reset by closing contacts in a relay circuit, the register counters being neutralized during this period. Only photo-multiplier signals of a certain magnitude are passed by a limiter circuit to the video circuits..The action and timing of the control circuits, i.e. marking register, reset and black white determination are described in detail in the Specification. The marking register (Fig. 30, not shown) comprises three sixteen-position shift registers made up of magnetic cores which store binary information, and each position is coded 1 or #1 so as to determine in the decoding circuits which of the coded 0-5 is appropriate for feeding to the programme rules circuit (Figs. 3F, 3G, 3H, not shown). Rule 1 circuit comprises an " OR " circuit 514 fed by a coded 0, 3 or 4 and an " AND " circuit 516 receiving the black lead B from Black White cable 388 and the output of the " OR " circuit, so that a coded 1 is fed back to the Encode circuit and the marking register, if a black signal follows a coded 0, 3 or 4. Rule 3 uses an " AND " circuit 518 to detect a white B following a coded 1 and feeds a coded 2 to the marking register. Rules 4-8 detect triple intersection, i.e. a black-whiteblack-white-black sequence, which is at least two bits wide. Primer trigger P 0 is " On " for the first black and Primer trigger P 1 is " on " if trigger P 0 is " on " and a white area is sensed. Similarly triggers P 2 , P 3 and P 4 go " On " for subsequent black and white sensings, and finally a memory trigger M 0 is in the " On " condition. Rule 9 detects the lower left inlet basic shape, requiring detection of triple intersection (M 0 is ON), and a coded 0 present in the lower of the two white areas. Connected to the input of the " AND " circuit of memory trigger M 1 are M 0 , P 0 in " On position (indicating passing of first black intercept), #P 2 in OFF position (second black not reached), an " in 0 " from Rule circuit input cable 460 and a fifth input lead #P 5 which determines that the presence of the lower inlet is detected after the detection of the triple intersection. Similarly the other memory triggers react to Rule circuits which indicate upper left inlet, lower and upper right inlet, lake basic shape, long vertical black line and the small left inlet, respectively. Other Rule circuits are utilized for the process of expanding and preventing imperfections in the numeral characters giving wrong indications, as, for example, serifs and other lines in the figures 7 and 2. As shown in Fig. 3I, the connections " M 0 "-" M 7 " from the memory triggers feed through relay drivers 574-581 to relays R 0 - R 7 controlling switches in the Christmas Tree Shape Decoder which determine which character is sensed, the O.K. to Punch signal on line 318 energizing the slow relay R 10 and line 414 to punch or print the character recognized.

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