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    2.
    发明专利
    未知

    公开(公告)号：DE3854384D1

    公开(公告)日：1995-10-05

    申请号：DE3854384

    申请日：1988-11-09

    Applicant: IBM

    Inventor： BLOUNT MARION LEE ,  COCCHI ANTHONY ,  MERGEN MARK FREDERICK ,  MORGAN STEPHEN PAUL ,  RADER KATALIN ANNA

    IPC: G06F12/08 ,  G06F9/46 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F12/00 ,  G06F12/10 ,  G06F15/16 ,  G06F15/177

    Abstract: A method for maintaining the overall system availability of a multi-processor data processing system in the event of a failure at one of a plurality of independent failure points. The system includes a plurality of virtual memory type processor units, each of which includes an interactive terminal, and a main memory which is connected to a secondary storage device which is also shared by the main memory of one of the other processor units. The main memories of the two units are also interconnected to provide a shared virtual memory system. Both processor units employ the same operating system and share the same virtual address space for storing information. The interactive terminal of each processor unit is connected to the other processor unit. Failure points include the terminals, the processor units, the communication links, and the various software components that are employed by the system. System availability is maintained by managing the storage of selected information at pre-established precise points in the processing operation. Identical operating system data structures that are stored in each processor unit are updated with the results of certain identified data processing transactions which have affected information required for succeeding processing operations in manner to insure that either identical updates occur or no update occurs. The arrangement ensures that any changes that might have occurred in the information stored in the data structure prior to the end of an aborted transaction is returned to the initial state to permit the transaction to be retried whenever the path of the failure can be bypassed.

    5.
    发明专利
    未知

    公开(公告)号：DE3577761D1

    公开(公告)日：1990-06-21

    申请号：DE3577761

    申请日：1985-06-03

    Applicant: IBM

    Inventor： COCKE JOHN ,  HAILPERN BRENT TZION ,  HOEVEL LEE WINDSOR ,  SHAPIRO EUGENE ,  BLOUNT MARION LEE

    IPC: G06F12/10 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  G06F15/173

    Abstract: A plurality of intelligent work stations (10) are provided access to a shared memory (12) through a switching hierarchy including a first array of mapping boxes (14) for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual address into a terminal switch port designation and logical address, a first switch (16) for forwarding the logical address and offset to the designated terminal switch port, a second array of mapping boxes (18) for receiving the logical address and offset and for I converting the logical address into a memory switch port designation and physical address, and a second switch (20) for forwarding the physical address and offset to the designated memory switch port as an address to the shared memory.

    7.
    发明专利
    未知

    公开(公告)号：BR8806305A

    公开(公告)日：1989-08-15

    申请号：BR8806305

    申请日：1988-11-30

    Applicant: IBM

    Inventor： BLOUNT MARION LEE ,  COCCHI ANTHONY ,  MERGEN MARK FREDERICK ,  MORGAN STEPHEN PAUL ,  RADER KATALIN ANNA VERONIKA

    IPC: G06F12/08 ,  G06F9/46 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F12/00 ,  G06F12/10 ,  G06F15/16 ,  G06F15/177 ,  G06F13/14

    Abstract: A method for maintaining the overall system availability of a multi-processor data processing system in the event of a failure at one of a plurality of independent failure points. The system includes a plurality of virtual memory type processor units, each of which includes an interactive terminal, and a main memory which is connected to a secondary storage device which is also shared by the main memory of one of the other processor units. The main memories of the two units are also interconnected to provide a shared virtual memory system. Both processor units employ the same operating system and share the same virtual address space for storing information. The interactive terminal of each processor unit is connected to the other processor unit. Failure points include the terminals, the processor units, the communication links, and the various software components that are employed by the system. System availability is maintained by managing the storage of selected information at pre-established precise points in the processing operation. Identical operating system data structures that are stored in each processor unit are updated with the results of certain identified data processing transactions which have affected information required for succeeding processing operations in manner to insure that either identical updates occur or no update occurs. The arrangement ensures that any changes that might have occurred in the information stored in the data structure prior to the end of an aborted transaction is returned to the initial state to permit the transaction to be retried whenever the path of the failure can be bypassed.

    9.
    发明专利
    未知

    公开(公告)号：DE3854384T2

    公开(公告)日：1996-03-28

    申请号：DE3854384

    申请日：1988-11-09

    Applicant: IBM

    Inventor： BLOUNT MARION LEE ,  COCCHI ANTHONY ,  MERGEN MARK FREDERICK ,  MORGAN STEPHEN PAUL ,  RADER KATALIN ANNA

    IPC: G06F12/08 ,  G06F9/46 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F12/00 ,  G06F12/10 ,  G06F15/16 ,  G06F15/177

    Abstract: A method for maintaining the overall system availability of a multi-processor data processing system in the event of a failure at one of a plurality of independent failure points. The system includes a plurality of virtual memory type processor units, each of which includes an interactive terminal, and a main memory which is connected to a secondary storage device which is also shared by the main memory of one of the other processor units. The main memories of the two units are also interconnected to provide a shared virtual memory system. Both processor units employ the same operating system and share the same virtual address space for storing information. The interactive terminal of each processor unit is connected to the other processor unit. Failure points include the terminals, the processor units, the communication links, and the various software components that are employed by the system. System availability is maintained by managing the storage of selected information at pre-established precise points in the processing operation. Identical operating system data structures that are stored in each processor unit are updated with the results of certain identified data processing transactions which have affected information required for succeeding processing operations in manner to insure that either identical updates occur or no update occurs. The arrangement ensures that any changes that might have occurred in the information stored in the data structure prior to the end of an aborted transaction is returned to the initial state to permit the transaction to be retried whenever the path of the failure can be bypassed.

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