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    Machine tool control system with edge generator
    2.
    发明授权
    Machine tool control system with edge generator 失效
    具有边缘发电机的机床工具控制系统

    公开(公告)号：US3591781A

    公开(公告)日：1971-07-06

    申请号：US3591781D

    申请日：1968-12-30

    Applicant: IBM

    Inventor： BRENZA JAMES G

    IPC: G05D3/12 ,  G05B19/33 ,  G05B19/39 ,  G05B19/41 ,  G05B19/4103 ,  G05B19/30

    CPC classification number: G05B19/39 ,  G05B19/41 ,  G05B19/4103 ,  G05B2219/34121

    Abstract: A machine tool control system wherein command-position signals (such as square waves) are generated without the use of linear interpolation logic. A number representing a position in time equivalent to each rise or fall of the command-position square wave is generated and placed in a position register, which is compared with a running reference counter. An equal-compare signal reverses the level of a binary trigger and signals the apparatus to supply another number to the position register. The output of the binary trigger is used to generate the commandposition square wave.

    VARIABLE ADDRESS MODE CACHE
    6.
    发明专利
    VARIABLE ADDRESS MODE CACHE 未知

    公开(公告)号：CA1283218C

    公开(公告)日：1991-04-16

    申请号：CA534687

    申请日：1987-04-14

    Applicant: IBM

    Inventor： BRENZA JAMES G

    IPC: G06F12/08 ,  G06F12/10

    Abstract: The disclosure provides a data processing system which contains a multi-level storage hierarchy, in which the two highest hierarchy levels (e.g. L1 and L2) are private (not shared) to a single CPU, in order to be in close proximity to each other and to the CPU. Each cache has a data line length convenient to the respective cache. A common directory and an L1 control array (L1CA) are provided for the CPU to access both the L1 and L2 caches. The common directory contains and is addressed by the CPU requesting logical addresses, each of which is either a real/absolute address or a virtual address, according to whichever address mode the CPU is in. Each entry in the directory contains a logical address representation derived from a logical address that previously missed in the directory. A CPU request "hits" in the directory if its requested address is in any private cache (e.g. in L1 or L2). A line presence field (LPF) is included in each directory entry to aid in determining a hit in the L1 cache. The L1CA contains L1 cache information to supplement the corresponding common directory entry; the L1CA is used during a L1 LRU castout, but is not the critical path of an L1 or L2 hit. A translation lookaside buffer (TLB) is not used to determine cache hits. The TLB output is used only during the infrequent times that a CPU request misses in the cache directory, and the translated address (i.e. absolute address) is then used to access the data in a synonym location in the same cache, or in main storage, or in the L1 or L2 cache in another CPU in a multiprocessor system using synonym/cross-interrogate directories.

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