公开(公告)号：US3434115A

公开(公告)日：1969-03-18

申请号：US3434115D

申请日：1966-07-15

Applicant: IBM

Inventor： CHOMICKI JOHN S

IPC: G04F1/00 ,  G05B19/414 ,  G06F1/04 ,  G06F1/14 ,  G06F9/00 ,  G06F9/48 ,  G08G1/08 ,  G11B13/00

CPC classification number: G06F9/4818 ,  G06F1/14

公开(公告)号：US3245003A

公开(公告)日：1966-04-05

申请号：US33201663

申请日：1963-12-20

Applicant: IBM

Inventor： CHOMICKI JOHN S

IPC: H03K3/282 ,  H03K5/135

CPC classification number: H03K5/135 ,  H03K3/2823

公开(公告)号：US3493679A

公开(公告)日：1970-02-03

申请号：US3493679D

申请日：1966-09-22

Applicant: IBM

Inventor： CHOMICKI JOHN S

IPC: H03L7/00 ,  H04L7/00 ,  H04L7/033 ,  H04L27/24

CPC classification number: H04L7/00 ,  H03L7/00 ,  H04L7/0331

公开(公告)号：US3267459A

公开(公告)日：1966-08-16

申请号：US24555062

申请日：1962-12-18

Applicant: IBM

Inventor： CHOMICKI JOHN S ,  CRITCHLOW DALE L

IPC: G06F13/38 ,  H03M1/00 ,  H04J99/00 ,  H04L5/04 ,  H04L7/027 ,  H04L25/48

CPC classification number: H04L5/04 ,  G06F13/38 ,  H03M1/00 ,  H03M1/18 ,  H04J15/00 ,  H04L7/027

公开(公告)号：CA836177A

公开(公告)日：1970-03-03

申请号：CA836177D

Applicant: IBM

Inventor： CRITCHLOW DALE L ,  CHOMICKI JOHN S

公开(公告)号：CA871352A

公开(公告)日：1971-05-18

申请号：CA871352D

Applicant: IBM

Inventor： CHOMICKI JOHN S

公开(公告)号：CA796881A

公开(公告)日：1968-10-15

申请号：CA796881D

Applicant: IBM

Inventor： CHOMICKI JOHN S

公开(公告)号：CA769152A

公开(公告)日：1967-10-10

申请号：CA769152D

Applicant: IBM

Inventor： CHOMICKI JOHN S

公开(公告)号：DE1226626B

公开(公告)日：1966-10-13

申请号：DEJ0024891

申请日：1963-12-10

Applicant: IBM

Inventor： CHOMICKI JOHN S ,  CRITCHLOW DALE L

IPC: G06F13/38 ,  H03M1/00 ,  H04J99/00 ,  H04L5/04 ,  H04L7/027 ,  H04L25/48

Abstract: 996,409. Telegraphy; multiplex pulse code signalling. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 21, 1963 [Dec. 18, 1962], No. 45925/63. Drawings to Specification. Headings H4L and H4P. In a data receiver to counteract drift in the clamping circuit that occurs when the data has one value for some time a D.C. feed-back path is provided from the output of the receiver to the input. In the embodiment described two binary messages are transmitted as a single 4-level message by adding one to the other doubled in amplitude. This message is preceded by a signal which causes a clamp in the receiver to place the received data at the correct level. The data is fed to threshold circuits which provide three signals indicative of the level of the data. These signals are fed to logic circuitry to derive output signals the equivalent of the original two binary messages. The outputs from the logic are combined to give a four-level signal which acts in the D.C. feed-back loop to stabilize the D.C. level at the receiver input.