公开(公告)号：CA2077048A1

公开(公告)日：1993-06-21

申请号：CA2077048

申请日：1992-08-27

Applicant: IBM

Inventor： DERWIN MICHAEL T ,  WALL WILLIAM A

IPC: G06F12/08

Abstract: A personal computer has a memory system including a write-through cache which is accessible by more than one device. A snoop mechanism includes logic that monitors bus master control signals to determine if a new memory write cycle has been started before a current snoop cycle has finished. If a new cycle has been started, then a corresponding snoop cycle occurs which overlaps the new memory cycle and is pipelined with the previous snoop cycle so that the snooping mechanism does not fall behind the memory write cycles.

公开(公告)号：BR9204884A

公开(公告)日：1993-06-22

申请号：BR9204884

申请日：1992-12-07

Applicant: IBM

Inventor： DERWIN MICHAEL T ,  WALL WILLIAM A

IPC: G06F12/08 ,  G06F15/40

Abstract: A personal computer has a memory system including a write-through cache which is accessible by more than one device. A snoop mechanism includes logic that monitors bus master control signals to determine if a new memory write cycle has been started before a current snoop cycle has finished. If a new cycle has been started, then a corresponding snoop cycle occurs which overlaps the new memory cycle and is pipelined with the previous snoop cycle so that the snooping mechanism does not fall behind the memory write cycles.