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    LOGIC ARRAY INCORPORATING JOSEPHSON DEVICES
    4.
    发明专利
    LOGIC ARRAY INCORPORATING JOSEPHSON DEVICES 未知

    公开(公告)号：DE3168558D1

    公开(公告)日：1985-03-14

    申请号：DE3168558

    申请日：1981-02-16

    Applicant: IBM

    Inventor： FARIS SADEG MUSTAFA

    IPC: G11C11/44 ,  H03K19/177 ,  H03K19/195

    Abstract: A Programmable Logic Array (PLA) system which utilizes Josephson devices and the noninverting capabilities of these devices is disclosed. The disclosed PLA system includes a personalized Read Only Memory (ROM) which is adapted to store the applied input signals as well as the output signals which are a logic function of the input signals. As soon as outputs from the ROM are available, an interface circuit which may be timed or untimed, inverting or noninverting provides output signals which can be utilized to drive other logic circuits or to act as inputs to another personalized Read Only Memory (ROM). The latter provides another logic function of the inputs at its outputs. Again, the outputs may be used directly or applied to another interface circuit which itself may provide inverted or noninverted outputs. Like the first mentioned ROM, the second mentioned ROM is capable of storing its inputs and the resulting outputs which are some logic function of the inputs as a result of the ROM personalization. The ROM's involved utilize memory cells which are programmable Josephson junction devices operating in a liquid helium environment. The programmable logic array system is disclosed in a full adder embodiment which is dc powered. A similar hybrid embodiment using both ac and dc power is also shown. The resulting system using high density ROM's provides high speed logic using relatively standard loop circuits which minimize the effect of the presence of resonances of known random logic circuits.

    JOSEPHSON-CONTACTS DIGITAL CURRENT AMPLIFIER
    5.
    发明专利
    JOSEPHSON-CONTACTS DIGITAL CURRENT AMPLIFIER 未知

    公开(公告)号：DE2964905D1

    公开(公告)日：1983-03-31

    申请号：DE2964905

    申请日：1979-08-21

    Applicant: IBM

    Inventor： FARIS SADEG MUSTAFA

    IPC: H03K3/38 ,  H03K5/00 ,  H03K17/92 ,  H03K19/195 ,  H03F19/00 ,  H01L39/22

    Abstract: A self-resetting digital current amplifier which utilizes Josephson devices is disclosed. The basic circuit includes a pair of switchable Josephson devices connected to each other and with an output load. The first of these devices is switched by a combination of control current and gate current. The second device is switched by a combination of gate current and current applied from an inductance which is connected between the bottom of the first Josephson device and the top of the second Josephson device. The circuit is fed by a single DC source. In the steady state, current flows from the DC source through the first of the Josephson devices to the second of the Josephson devices via the interconnecting inductance and from then back to the DC source. A pair of resistances in series with the second of the Josephson devices cause current to flow in the inductance which, in the steady state, is essentially a short circuit path. In the dynamic state, a control signal on the first of the Josephson devices in the presence of the gate current causes that device to switch diverting the gate current into the second Josephson device. When the first Josephson device switches, the inductance experiences a high rate of change of current and, in effect, acts as a second current source feeding the second of the Josephson devices along with the diverted gate current. The combination of these currents exceeds the threshold of the second Josephson device causing it to switch instantaneously and deliver the combined current to a load circuit. Any number of additional inductances and current switched Josephson devices may precede the load circuit and amplification is achieved which is a function of the number of inductances acting as current sources. The circuit is self-resetting because it has only one external source. Resetting of the circuit can be independent of the value of load impedance and, as such, can feed current to a high load impedance without sacrificing the ability to be self-resetting. In another embodiment, a plurality of cascaded circuits may be connected in parallel to feed a single load circuit with an extremely high current pulse. The use of delayed triggering and current cancellation can also provide extremely narrow high current pulses. Because of the self-resetting feature, repetition rates in the picosecond range are also achievable.

    7.
    发明专利
    未知

    公开(公告)号：DE2834236A1

    公开(公告)日：1979-05-23

    申请号：DE2834236

    申请日：1978-08-04

    Applicant: IBM

    Inventor： FARIS SADEG MUSTAFA

    IPC: G11C11/44 ,  G11C7/00

    Abstract: A number of memory array configurations which avoid a spurious half-select condition in unselected cells of a superconducting memory array is disclosed. The memory arrays incorporate memory cells which include at least single Josephson junction disposed in a superconducting loop wherein binary information is stored in the form of at least one circulating current. By providing means for applying a control magnetic field to only the selected memory cell, spurious writing of an unselected memory cell is avoided. This is accomplished in a number of embodiments by causing the application of the half-select current (which normally provides the control magnetic field to a memory cell) to divert a previously applied half-select or enabling current to the memory cell into another path so that the previously applied half-select or enabling current now acts as a control current for switching the storage gate of the selected memory cell. Diverson of the enabling current is, in turn, achieved by the switching of a serially disposed Josephson device which switches in response to the presence of two half-select currents in that device. Any othersimilarly serially disposed device in an unselected memory cell encounters only a single half-select current and, under such circumstances, cannot switch to control its associated storage gate. Any other unselected cell encounters, at most, a single half-select current.

    HIGH RESOLUTION SUPERCONDUCTIVE SAMPLING SYSTEM
    9.
    发明专利
    HIGH RESOLUTION SUPERCONDUCTIVE SAMPLING SYSTEM 未知

    公开(公告)号：DE3067698D1

    公开(公告)日：1984-06-07

    申请号：DE3067698

    申请日：1980-09-15

    Applicant: IBM

    Inventor： FARIS SADEG MUSTAFA

    IPC: G11C27/02 ,  G01R13/34 ,  G01R29/027 ,  H01L39/22 ,  H03K7/02 ,  H03K17/92 ,  G01R29/02

    Abstract: A circuit is provided for sampling and accurately reproducing unknown signals with picosecond resolution, which could be electrical, optical, X-ray, gamma ray, or particle signals. The circuit comprises a superconductive monitor gate having at least two states which are distinguishable from one another. The monitor gate could be, for example, comprised of a Josephson device or a superconducting quantum interference device (SQUID). Switching means, including a source of the unknown signal, are provided to switch the state of the monitor gate. This switching means includes a sampling pulse source and a bias current source which are combined with the unknown signal to change the state of the monitor gate. A noise elimination means is also provided including a lock-in amplifier, a comparator, and a feedback loop. A time averaging technique eliminates any incorrect indications resulting from noise. A timing means establishes a timing reference and sampling delay, and includes the sampling pulse source, delay lines, and a trigger pulse source connected to the source of the unknown signal and to the sampling pulse source. A display, such as an x-y recorder or oscilloscope, indicates the unknown signal. The circuit has applications in all devices where fast unknown waveform must be measured exactly, and in the field of non-equilibrium superconductivity, where exceptionally high resolution and sensitivity are required.

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