-
公开(公告)号：WO2004053697A3
公开(公告)日：2006-01-05
申请号：PCT/GB0305331
申请日：2003-12-05
Inventor： CASTELLI VITTORIO , FRANASZEK PETER , POFF DAN , SCHULZ CHARLES
CPC classification number: H03M7/30 , G06F12/08 , G06F12/10 , G06F2212/401 , Y10S707/99942
Abstract: In a computer system having a main memory for storing data in a compressed format and a processor cache for storing decompressed data, a method for converting the data of said main memory from compressed to uncompressed state, comprising the steps of a) reducing used portions of said main memory to a target value; b) disabling a compressor used for compressing the uncompressed data; c) decompressing said compressed data of said main memory; d) moving said decompressed data to physical addresses equal to real addresses; e) and releasing the memory occupied by a compressed memory director and data structures used in steps a. to d.
Abstract translation: 在具有以压缩格式存储数据的主存储器和用于存储解压缩数据的处理器高速缓存的计算机系统中，一种用于将所述主存储器的数据从压缩状态转换成非压缩状态的方法，包括以下步骤：a）减少使用的部分 主要记忆为目标值; b）禁用用于压缩未压缩数据的压缩器; c）解压缩所述主存储器的所述压缩数据; d）将所述解压缩数据移动到等于实际地址的物理地址; e）并释放由压缩存储器引导器占用的存储器和在步骤a中使用的数据结构。 到d
-
公开(公告)号：WO2004057479A3
公开(公告)日：2004-12-23
申请号：PCT/GB0305401
申请日：2003-12-11
Inventor： FRANASZEK PETER
IPC: G06F12/08
CPC classification number: G06F12/0862 , G06F2212/6022 , G06F2212/6024
Abstract: A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controlling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.
Abstract translation: 一种用于增强高速缓存预取行为的计算机系统和方法。 一种包括处理器，主存储器，预取控制器，高速缓冲存储器，预取缓冲器和主存储器的计算机系统，其中主存储器中的每个页面都具有与其关联的标签，该标签用于控制预取 来自此页面的可变行子集以及来自至少一个其他页面的行。 并且，与处理器耦合的是预取控制器，其中预取控制器响应于处理器通过相应标签获取相应的数据行来确定一行数据发生的故障（或未命中），其中相应的标签为 存储在预取缓冲区中，并将相应的数据行发送到高速缓冲存储器。
-
公开(公告)号：JP2005302034A
公开(公告)日：2005-10-27
申请号：JP2005115147
申请日：2005-04-12
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： FRANASZEK PETER , LASTRAS LUIS A
CPC classification number: G06F12/0862 , G06F12/0895 , G06F2212/1024 , G06F2212/502 , G06F2212/6022 , G06F2212/6024
Abstract: PROBLEM TO BE SOLVED: To provide a system and method for memory management.
SOLUTION: A system for memory management includes a tag controlled buffer in communication with a memory device. The memory device includes a plurality of pages divided into a plurality of individually addressable lines. The tag controlled buffer includes a prefetch buffer including at least one of the individually addressable lines form the memory device. The tag controlled buffer also includes a tag cache in communication with the prefetch buffer. The tag cache includes a plurality of tags, where each tag is associated with one of the pages in the memory device and each tag includes a pointer to at least one of the lines in the prefetch buffer. Access to the lines in the prefetch buffer is controlled by the tag cache.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供用于存储器管理的系统和方法。 解决方案：用于存储器管理的系统包括与存储器件通信的标签控制缓冲器。 存储装置包括被分成多个可单独寻址的行的多个页面。 标签控制缓冲器包括预取缓冲器，其包括形成存储器件的单独可寻址线中的至少一个。 标签控制缓冲器还包括与预取缓冲器通信的标签缓存。 标签缓存包括多个标签，其中每个标签与存储器设备中的一个页面相关联，并且每个标签包括指向预取缓冲器中的至少一行的指针。 访问预取缓冲区中的行由标记缓存控制。 版权所有（C）2006，JPO＆NCIPI
-
公开(公告)号：CA2511752A1
公开(公告)日：2004-06-24
申请号：CA2511752
申请日：2003-12-05
Applicant: IBM
Inventor： FRANASZEK PETER , CASTELLI VITTORIO , POFF DAN , SCHULZ CHARLES
Abstract: In a computer system having a main memory for storing data in a compressed format and a processor cache for storing decompressed data, a method for converting the data of said main memory from compressed to uncompressed stat e, comprising the steps of reducing used portions of said main memory to a targ et value; disabling a compressor used for compressing the uncompressed data; decompressing said compressed data of said main memory; moving said decompressed data to physical addresses equal to real addresses; and releasi ng the memory occupied by a compressed memory director and data structures used in steps a. to d.
-
公开(公告)号：AT507617T
公开(公告)日：2011-05-15
申请号：AT03767965
申请日：2003-12-05
Applicant: IBM
Inventor： CASTELLI VITTORIO , FRANASZEK PETER , POFF DAN , SCHULZ CHARLES
Abstract: A computer system having a main memory for storing data in a compressed format and a processor cache for storing decompressed data, a method for converting the data of said main memory from compressed to uncompressed state, comprising the steps of reducing used portions of said main memory to a target value; disabling a compressor used for compressing the uncompressed data; decompressing said compressed data of said main memory; moving said decompressed data to physical addresses equal to real addresses; and releasing the memory occupied by a compressed memory director and data structures used in the above steps.
-
Patent Agency Ranking
公开(公告)号：AU2003292388A1
公开(公告)日：2004-06-30
申请号：AU2003292388
申请日：2003-12-05
Applicant: IBM
Inventor： CASTELLI VITTORIO , FRANASZEK PETER , POFF DAN , SCHULZ CHARLES
Abstract: A computer system having a main memory for storing data in a compressed format and a processor cache for storing decompressed data, a method for converting the data of said main memory from compressed to uncompressed state, comprising the steps of reducing used portions of said main memory to a target value; disabling a compressor used for compressing the uncompressed data; decompressing said compressed data of said main memory; moving said decompressed data to physical addresses equal to real addresses; and releasing the memory occupied by a compressed memory director and data structures used in the above steps.
-
公开(公告)号：AT475140T
公开(公告)日：2010-08-15
申请号：AT03780378
申请日：2003-12-11
Applicant: IBM
Inventor： FRANASZEK PETER
IPC: G06F12/08
-
公开(公告)号：AU2003292388A8
公开(公告)日：2004-06-30
申请号：AU2003292388
申请日：2003-12-05
Applicant: IBM
Inventor： POFF DAN , CASTELLI VITTORIO , SCHULZ CHARLES , FRANASZEK PETER
Abstract: A computer system having a main memory for storing data in a compressed format and a processor cache for storing decompressed data, a method for converting the data of said main memory from compressed to uncompressed state, comprising the steps of reducing used portions of said main memory to a target value; disabling a compressor used for compressing the uncompressed data; decompressing said compressed data of said main memory; moving said decompressed data to physical addresses equal to real addresses; and releasing the memory occupied by a compressed memory director and data structures used in the above steps.
-
">
公开(公告)号：DE60336929D1
公开(公告)日：2011-06-09
申请号：DE60336929
申请日：2003-12-05
Applicant: IBM
Inventor： CASTELLI VITTORIO , FRANASZEK PETER , POFF DAN , SCHULZ CHARLES
-
公开(公告)号：DE60333483D1
公开(公告)日：2010-09-02
申请号：DE60333483
申请日：2003-12-11
Applicant: IBM
Inventor： FRANASZEK PETER
IPC: G06F12/08
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.019 seconds)
