公开(公告)号：EP1952289A4

公开(公告)日：2009-07-29

申请号：EP06816698

申请日：2006-10-11

Applicant: IBM

Inventor： MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  GRAUR IOANA ,  KRASNOPEROVA AZALIA

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.

公开(公告)号：JP2008139843A

公开(公告)日：2008-06-19

申请号：JP2007273995

申请日：2007-10-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GRAUR IOANA ,  BAUM ZACHARY ,  SCOTT M MANSFIELD ,  LIEBMANN LARS W

IPC: G03F1/08

CPC classification number: G03F1/36

Abstract: PROBLEM TO BE SOLVED: To provide an effective OPC technique, using a hierarchical data structure for designing a high-density mask that requires coloring. SOLUTION: A mask layout that requires coloring, such as, alternating phase shift mask, double-exposure mask and double-exposure etching mask is organized into uncolored hierarchical design units. Each hierarchical design unit is colored locally. Then, OPC is performed on the locally colored hierarchical design unit; the local coloring information for the OPC-modified design unit is discarded; after OPC modification, the uncolored OPC-modified design unit is placed within the mask layout, and the flattened data are colored; turnaround time for mask design is improved significantly, since the need to perform OPC on flattened data is avoided, while less intensive global coloring is performed on flattened data. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供有效的OPC技术，使用分层数据结构来设计需要着色的高密度掩模。

解决方案：需要着色的掩模布局，例如交替相移掩模，双曝光掩模和双曝光蚀刻掩模被组织成无色层级设计单元。 每个分级设计单元都在本地着色。 然后，在本地着色的分层设计单元上执行OPC; OPC设计单元的局部着色信息被丢弃; OPC修改后，将未修饰的OPC修改后的设计单元放置在掩模布局中，并将平坦化的数据着色; 掩模设计的周转时间大大提高，因为避免了在平坦化数据上执行OPC的需要，而对扁平化数据执行较少强化的全局着色。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2005037945A

公开(公告)日：2005-02-10

申请号：JP2004207387

申请日：2004-07-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LIEBMANN LARS W ,  BUKOFSKY SCOTT J ,  GRAUR IOANA

IPC: G03F1/08 ,  G03C3/02 ,  G03C5/00 ,  G03F1/00 ,  G03F9/00 ,  G06F17/50 ,  H01L21/027

CPC classification number: G03F1/30 ,  G03F1/70

Abstract: PROBLEM TO BE SOLVED: To provide a method and an apparatus for generating a mask pattern for alternating phase-shift mask lithography.
SOLUTION: The method for generating patterns of a pair of photomasks from a data set defining a circuit layout to be realized on a substrate includes identifying critical segments of the circuit layout to be realized on the substrate. Block mask patterns are generated and then legalized based on the identified critical segments. Thereafter, phase mask patterns are generated, legalized and colored. The legalized block mask patterns and the legalized phase mask patterns that have been colored define features of a block mask and an alternating phase shift mask, respectively, for use in a dual exposure method for patterning features in a resist layer of the substrate.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于产生用于交替相移掩模光刻的掩模图案的方法和装置。 解决方案：用于从定义要在基板上实现的电路布局的数据集中产生一对光掩模的图案的方法包括识别要在基板上实现的电路布局的关键段。 生成块掩码模式，然后根据所识别的关键段进行合法化。 此后，生成相位掩模图案，合法化和着色。 已经着色的合法化块掩模图案和合法化的相位掩模图案分别定义了块掩模和交替相移掩模的特征，用于在衬底的抗蚀剂层中构图特征的双曝光方法中。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2006011447A

公开(公告)日：2006-01-12

申请号：JP2005184783

申请日：2005-06-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GRAUR IOANA ,  YANG O KIM ,  MARK A RABIN ,  LAAS W LIEBMANN

IPC: G03F1/08 ,  G03F1/00 ,  G06F17/50

CPC classification number: G03F1/30

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for designing an Levenson type phase shifting mask with which the phase shape collision within a design layout can be solved. SOLUTION: The method of designing the Lvenson type phase shifting mask for projecting an image of an integrated circuit design is provided. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e.g., be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于设计在设计布局中相位形状碰撞的莱文森型相移掩模的改进方法。 提供了设计用于投影集成电路设计的图像的Lvenson型移相掩模的方法。 相位单元在分层电路设计的每个单元内是二进制可着色的，例如单元，阵列，网络或网络和/或单元阵列。 分层单位内的相位或颜色的分配将被正确地二进制着色以满足平版印刷，可制造性和其他设计规则，统称为着色规则。 在与其他单元的组装期间，层级单元中的相位的着色可能改变（例如，被颠倒或翻转），但是保留了分层单元的正确的二值可着色性，这简化了集成电路布局的组装。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2008055195A3

公开(公告)日：2008-08-07

申请号：PCT/US2007083145

申请日：2007-10-31

Applicant: IBM ,  MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  GRAUR IOANA ,  HAN GENG

Inventor： MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  GRAUR IOANA ,  HAN GENG

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A method of designing an integrated circuit is provided in which the design layout is optimized using a process model (54) until the design constraints (11) are satisfied by the image contours (51) simulated by the process model (54). The process model (54) used in the design phase need not be as accurate as the lithographic model (61) used in preparing the lithographic mask layout during data prep. The resulting image contours (51) are then included with the modified, optimized design layout to the data prep process (60), in which the mask layout is optimized using the lithographic process model (61), for example, including RET and OPC. The mask layout optimization (60) matches the images simulated by the lithographic process model (61) with the image contours (51) generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout (60).

Abstract translation: 提供一种设计集成电路的方法，其中使用过程模型（54）优化设计布局，直到由过程模型（54）模拟的图像轮廓（51）满足设计约束（11）。 在设计阶段使用的过程模型（54）不需要与在数据准备期间制备光刻掩模布局时使用的光刻模型（61）一样精确。 然后将所得图像轮廓（51）与经修改的优化设计布局一起包括到数据准备过程（60）中，其中使用例如包括RET和OPC的光刻过程模型（61）来优化掩模布局。 掩模版图优化（60）将由光刻工艺模型（61）模拟的图像与在设计阶段期间生成的图像轮廓（51）相匹配，这确保由设计者指定的设计和可制造性约束通过优化掩模 布局（60）。