PROCESSOR I/O INTERRUPT FILTER
    1.
    发明专利

    公开(公告)号:PH23471A

    公开(公告)日:1989-08-07

    申请号:PH33295

    申请日:1986-01-17

    Applicant: IBM

    Abstract: Data processing system including a main processor (11) and a co-processor (22) sharing the same I/O facilities (17,18,19) as the main processor (11) and running software unknown to the main processor (11). The main processor (11) can concurrently run other software and maintains priority over shared I/O facilities (17,18,19) by providing trapping logic incorporated in a random access memory and dynamically loadable by the main processor (11) which contains data related to the current useability by the co-processor (22) of a shared I/O device (17). Additional logic is associated with the co-processor (22) to manage interrupts between the co-processor (22) and the system bus (16).

    DRYING OF INK ON PRINT MEDIA
    2.
    发明专利

    公开(公告)号:AU533235B2

    公开(公告)日:1983-11-10

    申请号:AU6084880

    申请日:1980-07-28

    Applicant: IBM

    Abstract: A printer has a sheet feed and drum transport assembly (17), an exit assembly (465) and a dryer. Various print parameters or conditions relating to the drying of the ink on the print medium are monitored. These print parameters include print data density, ink drying characteristics and ambient humidity. The monitored print parameters are used to control the drying. In addition the monitored print parameters are used to control the detaching of the print medium from a rotary transport drum (10).

    IMPROVEMENTS IN DATA TRANSFER APPARATUS

    公开(公告)号:GB1282393A

    公开(公告)日:1972-07-19

    申请号:GB2247871

    申请日:1971-04-19

    Applicant: IBM

    Abstract: 1282393 Digital data transfer INTERNATIONAL BUSINESS MACHINES CORP 19 April 1971 [5 March 1970] 22478/71 Heading G4C A digital electric data transfer apparatus in which a byte of data comprises a number of bits transferred in parallel, comprises a deskewing means 12 for assembling bytes, a byte assembly counter 15 for counting the number of bytes assembled, a byte output counter 16 for counting the number of bytes transferred, and means for initiating transfer when the counter 15 holds a greater count than counter 16. Apparatus.-Data is stored on magnetic tape 10 or other means, transferred to the deskewing means 12 (SKB) and thence to a data channel 17. The SKB is a modification of the SKB in British Patent No. 902,164 and has a plurality of read in counters 13 (RIC), one for each bit of a data byte being transferred. The byte assembly counter 15 (BAC) is responsive to the RIC and counts the number of assembled bytes, and the byte output counter 16 (BOC) counts the number of bytes transferred from the SKB to channel 17 via buffer 18. A clock 20 controls operations. Operation.-Every time channel 17 is ready to receive data and compare circuit 22 indicates that the BOC count is less than the BAC count (i.e. there is a byte ready for transfer) the clock 20 is activated. Firstly buffer 18 is cleared then a byte is transferred from the SKB to the buffer. The byte is the oldest in the SKB and is determined by the tally in BOC 16. BOC 16 is then incremented and line 31 activated to determine if BAC 15 is zero. Skew check (Fig. 2, not shown).-Circuit 40 receives the counts from the respective RIC's and, if there is too great a difference between the tallies, there is excessive skew. Overrun check.-Circuit 41 indicates overrun (i.e. more bytes entering the apparatus than leaving so that it is overfull) when the BOC has a predetermined relationship with the leading RIC. The overrun and skew checks do not take part simultaneously and if overrun or excessive skew is detected a diagnostic routine is entered.

    A DATA PROCESSING SYSTEM
    5.
    发明专利

    公开(公告)号:IN166350B

    公开(公告)日:1990-04-14

    申请号:IN858MA1985

    申请日:1985-10-28

    Applicant: IBM

    Abstract: Data processing system including a main processor (11) and a co-processor (22) sharing the same I/O facilities (17,18,19) as the main processor (11) and running software unknown to the main processor (11). The main processor (11) can concurrently run other software and maintains priority over shared I/O facilities (17,18,19) by providing trapping logic incorporated in a random access memory and dynamically loadable by the main processor (11) which contains data related to the current useability by the co-processor (22) of a shared I/O device (17). Additional logic is associated with the co-processor (22) to manage interrupts between the co-processor (22) and the system bus (16).

    8.
    发明专利
    未知

    公开(公告)号:AT20216T

    公开(公告)日:1986-06-15

    申请号:AT80101466

    申请日:1980-03-20

    Applicant: IBM

    Abstract: In a printing device including a paper feed drum 10 and a printing array 250, the movements of the drum and array are controlled by servo systems 62 and 264. Both servo loops include a common micro-processor. During a non-printing cycle of the machine, the processor selects certain operating parameters and stores these parameters as critical operating parameters for use in subsequent printing cycles.

    9.
    发明专利
    未知

    公开(公告)号:FI801324A

    公开(公告)日:1980-10-31

    申请号:FI801324

    申请日:1980-04-24

    Applicant: IBM

    Abstract: In a printing device including a paper feed drum 10 and a printing array 250, the movements of the drum and array are controlled by servo systems 62 and 264. Both servo loops include a common micro-processor. During a non-printing cycle of the machine, the processor selects certain operating parameters and stores these parameters as critical operating parameters for use in subsequent printing cycles.

    PLURAL PROCESSOR SYSTEMS HAVING SHARED RESOURCES

    公开(公告)号:GB2171823B

    公开(公告)日:1989-06-14

    申请号:GB8525990

    申请日:1985-10-22

    Applicant: IBM

    Abstract: Data processing system including a main processor (11) and a co-processor (22) sharing the same I/O facilities (17,18,19) as the main processor (11) and running software unknown to the main processor (11). The main processor (11) can concurrently run other software and maintains priority over shared I/O facilities (17,18,19) by providing trapping logic incorporated in a random access memory and dynamically loadable by the main processor (11) which contains data related to the current useability by the co-processor (22) of a shared I/O device (17). Additional logic is associated with the co-processor (22) to manage interrupts between the co-processor (22) and the system bus (16).

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