公开(公告)号：ZA7502023B

公开(公告)日：1976-11-24

申请号：ZA7502023

申请日：1975-04-01

Applicant: IBM

Inventor： JONES JOHN WYN ,  JOHN WYN JONES

IPC: G06F7/00 ,  G06F7/57 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/40 ,  G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  H03K

CPC classification number: G06F11/2051 ,  G06F9/223 ,  G06F9/26 ,  G06F9/4484

Abstract: A universal array logic module featuring autonomous operation includes interconnected array structured logic and a small writable storage array. The module is subject to large scale integrated packaging as a standardly dimensioned unit (e.g. chip). The internal connections form discrete first and second internal circulation loops in one of which the storage array connects as a serial constituent randomly addressable by signals carried in the other loop. The storage array typically holds eight 32-bit words. The logic arrays may be read-only structures organized to perform arithmetic and translational logic manipulations under autonomous (internal) control. The module assembly includes integral input/output gating for transferring signals between an external bus and the internal loops. The logic array structure permits both external and internal control of cyclic operation. The operation repertoire includes interrupts, resets, and sequence branches. Interrupted status (loop signals) is saved in predetermined address locations of the storage array, requiring novel manipulation and storage of the address argument of the interrupted cycle. The logic arrays may be economically configured as read-only structures.

公开(公告)号：CH536000A

公开(公告)日：1973-05-30

申请号：CH536000D

申请日：1972-07-18

Applicant: IBM

Inventor： JOHN WYN JONES ,  KEITH G TAYLOR ,  DAVID J CRAFT

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/06

公开(公告)号：CH518597A

公开(公告)日：1972-01-31

申请号：CH523670

申请日：1970-04-09

Applicant: IBM

Inventor： MICHAEL FLINDERS ,  PETER LYCETT GARDNER ,  MICHAEL HENRY HALLETT ,  JOHN WYN JONES ,  JOHN FRANCIS MINSHULL ,  KEITH GRAHAM TAYLOR

IPC: G06F12/16 ,  G06F11/16 ,  G11C15/04 ,  G06F11/00 ,  H04L1/00

公开(公告)号：ZA752023B

公开(公告)日：1976-11-24

申请号：ZA752023

申请日：1975-04-01

Applicant: IBM

Inventor： JONES JOHN WYN ,  JOHN WYN JONES

IPC: G06F7/57 ,  G06F7/00 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/40 ,  G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  H03K

Abstract: A universal array logic module featuring autonomous operation includes interconnected array structured logic and a small writable storage array. The module is subject to large scale integrated packaging as a standardly dimensioned unit (e.g. chip). The internal connections form discrete first and second internal circulation loops in one of which the storage array connects as a serial constituent randomly addressable by signals carried in the other loop. The storage array typically holds eight 32-bit words. The logic arrays may be read-only structures organized to perform arithmetic and translational logic manipulations under autonomous (internal) control. The module assembly includes integral input/output gating for transferring signals between an external bus and the internal loops. The logic array structure permits both external and internal control of cyclic operation. The operation repertoire includes interrupts, resets, and sequence branches. Interrupted status (loop signals) is saved in predetermined address locations of the storage array, requiring novel manipulation and storage of the address argument of the interrupted cycle. The logic arrays may be economically configured as read-only structures.