公开(公告)号：EP2113109A4

公开(公告)日：2010-04-21

申请号：EP07865915

申请日：2007-12-20

Applicant: IBM

Inventor： KRASNOPEROVA AZALIA

IPC: G06F17/50 ,  G03F1/14

CPC classification number: G03F1/36

公开(公告)号：EP1952289A4

公开(公告)日：2009-07-29

申请号：EP06816698

申请日：2006-10-11

Applicant: IBM

Inventor： MANSFIELD SCOTT M ,  LIEBMANN LARS W ,  GRAUR IOANA ,  KRASNOPEROVA AZALIA

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.