公开(公告)号：SG43737A1

公开(公告)日：1997-11-14

申请号：SG1996000346

申请日：1993-03-05

Applicant: IBM

Inventor： GONZALES CESAR AUGUSTO ,  HORVATH THOMAS AKOS ,  KREITZER NORMAN HENRY ,  LEAN ANDY GENG-CHYUN ,  MCCARTHY THOMAS

IPC: G06F17/14 ,  G06T1/20 ,  G06F9/38 ,  G06T1/60 ,  G06T9/00 ,  H04N7/26 ,  H04N7/30 ,  H04N7/32 ,  H04N7/50 ,  H04N7/54 ,  G06F15/66 ,  G06F15/64

Abstract: A sequential process-pipeline (12) has a first processing stage (30) coupled to a CODEC (24) through a plurality of buffers, including an image data input buffer (28), an image data output buffer (26), and an address buffer (34). The address buffer stores addresses, each of which identifies an initial address of a block of addresses within an image memory (22). Each block of addresses in the image memory stores a block of decompressed image data. A local controller (18) is responsive to the writing of an address into the address buffer to initiate the operation of the CODEC to execute a Discrete Cosine Transformation Process and a Discrete Cosine Transformation Quantization Process.