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    BUS INTERFACE DEVICE FOR A DATA PROCESSING SYSTEM
    1.
    发明专利
    BUS INTERFACE DEVICE FOR A DATA PROCESSING SYSTEM 未知

    公开(公告)号：DE3375611D1

    公开(公告)日：1988-03-10

    申请号：DE3375611

    申请日：1983-03-29

    Applicant: IBM ,  IBM FRANCE

    Inventor： RISO VLADIMIR ,  KUHNE ROLAND

    IPC: G06F13/36 ,  G06F13/42 ,  H04L25/24 ,  H04L25/52

    Abstract: A number (e.g. sixteen) of processors are connected to a central control unit by a common bus having half that number of wires (D0-D7) reserved for a byte of data or control bits, one line for a parity bit and one for a control bit. In the bus interface each line (D0-D7) is associated with two flip-flops (40,41) having direct and inverted (44) inputs of a first clock signal (CLK1). When received bits are in NRZ code with duration equal to half the clock period, output OR gates (47) reproduce resynchronised input bits. Processors divided into two equal gps. request access during one or other phase of a second clock signal. The state of access requests is indicated by memory flip-flops (48,49) when the bus is free.

    3.
    发明专利
    未知

    公开(公告)号：DE2855722A1

    公开(公告)日：1979-07-12

    申请号：DE2855722

    申请日：1978-12-22

    Applicant: IBM

    Inventor： EPENOY GABRIEL IRENEE ,  KUHNE ROLAND ,  LAURENT BERNARD ,  THIRION PHILIPPE

    IPC: G06F7/53 ,  G06F7/48 ,  G06F7/506 ,  G06F7/508 ,  G06F7/527 ,  G06F7/533 ,  G06F7/544 ,  G06F17/16 ,  G06F7/52

    Abstract: A specialized processor capable of computing a sum of products S= SIGMA +/-Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j= 2ROOT -1. The processor includes an instruction storage, means for decoding instructions read out of said storage and for controlling the operation of the processor, a data storage, and a multiplication and accumulation unit which has two multiplier-accumulator devices and several buffers for storing the operands Ai, Bi, Ci and Di sequentially read out of data storage. The real part Ai and the imaginary part Bi of the multiplier are respectively applied to the Multiplier inputs of the multiplier-accumulator devices and the real part Ci of the multiplicand is applied to the Multiplicand inputs of the multiplier-accumulator devices, which simultaneously compute the products Ai Ci and Bi Ci. The imaginary part Di of the multiplicand is then applied to the Multiplicand inputs of the multiplier-accumulator devices. The first of these then computes the product Bi Di and adds the same to the product Ai Ci, while the second device computes the product Ai Di and adds the same to the product Bi Ci to simultaneously provide the real and imaginary parts of the product Pi.

    6.
    发明专利
    未知

    公开(公告)号：FR2413712A1

    公开(公告)日：1979-07-27

    申请号：FR7739966

    申请日：1977-12-30

    Applicant: IBM FRANCE

    Inventor： EPENOY GABRIEL ,  KUHNE ROLAND ,  LAURENT BERNARD ,  THIRION PHILIPPE

    IPC: G06F7/53 ,  G06F7/48 ,  G06F7/506 ,  G06F7/508 ,  G06F7/527 ,  G06F7/533 ,  G06F7/544 ,  G06F17/16 ,  G06F7/38

    Abstract: A specialized processor capable of computing a sum of products S= SIGMA +/-Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j= 2ROOT -1. The processor includes an instruction storage, means for decoding instructions read out of said storage and for controlling the operation of the processor, a data storage, and a multiplication and accumulation unit which has two multiplier-accumulator devices and several buffers for storing the operands Ai, Bi, Ci and Di sequentially read out of data storage. The real part Ai and the imaginary part Bi of the multiplier are respectively applied to the Multiplier inputs of the multiplier-accumulator devices and the real part Ci of the multiplicand is applied to the Multiplicand inputs of the multiplier-accumulator devices, which simultaneously compute the products Ai Ci and Bi Ci. The imaginary part Di of the multiplicand is then applied to the Multiplicand inputs of the multiplier-accumulator devices. The first of these then computes the product Bi Di and adds the same to the product Ai Ci, while the second device computes the product Ai Di and adds the same to the product Bi Ci to simultaneously provide the real and imaginary parts of the product Pi.

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