公开(公告)号：JP2005311367A

公开(公告)日：2005-11-04

申请号：JP2005119125

申请日：2005-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DORIS BRUCE B ,  GUARINI KATHRYN W ,  LEONG MEIKEI ,  NARASIMHA SHREESH ,  REZNICEK ALEXANDER ,  KERN LIM ,  SADANA DEVENDRA K ,  SHI LEATHEN ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor device formed on a substrate having different crystal orientation.
SOLUTION: A method of forming a hybrid substrate containing strained Si and a strained Si containing hybrid substrate formed by this method are provided. In the present invention, a strained Si layer is formed on a semiconductor material, a second semiconductor layer, or both of them. According to the present invention, the strained Si layer has the same crystal orientation as either of a regrown semiconductor layer or the second semiconductor layer. This method provides the hybrid substrate wherein at least one of device layers contains the strained Si.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供形成在具有不同晶体取向的基板上的集成半导体器件。 解决方案：提供一种形成含有应变Si的混合基板和通过该方法形成的包含应变的含Si混合基板的方法。 在本发明中，在半导体材料，第二半导体层或它们两者上形成应变Si层。 根据本发明，应变Si层具有与重新生长的半导体层或第二半导体层中的任一个相同的晶体取向。 该方法提供混合基板，其中装置层中的至少一个包含应变Si。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006049897A

公开(公告)日：2006-02-16

申请号：JP2005219835

申请日：2005-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAINE C BOYD ,  HOLT JUDSON R ,  LEONG MEIKEI ,  MO RENEE T ,  REN ZHIBIN ,  SHAHIDI GHAVAM G

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/823892 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a super-steep retrograde well field effect transistor device, and to provide an ultra-thin body FET device manufactured by the same.
SOLUTION: The method for manufacturing a super-steep retrograde well field effect transistor device starts with an SOI layer formed on a substrate, for example, an embedded oxide layer. The SOI layer is thinned so as to form an ultra-thin SOI layer. A separation trench is formed for dividing the SOI layer into an N ground layer region and a P ground layer region. The N and P ground layer regions formed in the SOI layer are doped with N-type and P-type dopants to a high concentration level. A semiconductor channel region is formed on the N and P ground layer regions. The source region and the drain region of the FET and the gate electrode stack on the channel region are formed. As desired, a diffusion retarding layer is formed between the SOI ground layer regions and the channel regions.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造超陡逆向井场效应晶体管器件的方法，并提供由其制造的超薄体FET器件。 解决方案：用于制造超陡逆向井场效应晶体管器件的方法从形成在衬底上的SOI层，例如嵌入的氧化物层开始。 SOI层被薄化以形成超薄SOI层。 形成分离沟槽，用于将SOI层分成N个接地层区域和P个接地层区域。 形成在SOI层中的N和P接地层区域以高浓度水平掺杂有N型和P型掺杂剂。 在N和P接地层区域上形成半导体沟道区。 形成FET的源极区域和漏极区域以及沟道区域上的栅电极堆叠。 根据需要，在SOI接地层区域和沟道区域之间形成扩散延迟层。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2006057645A8

公开(公告)日：2006-08-03

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

Abstract translation: 本发明提供具有增强的电子和空穴迁移率的半导体材料，其包含具有110晶向和双向压缩应变的含有层。 术语“双轴压缩应力”在本文中用于描述由在制造半导体材料期间在含Si层上感应的纵向压缩应力和横向应力引起的净应力。 本发明的另一方面涉及一种形成本发明的半导体材料的方法。 本发明的方法包括提供含硅110层的步骤; 并在含硅110层中产生双轴应变。

公开(公告)号：JP2005136410A

公开(公告)日：2005-05-26

申请号：JP2004310704

申请日：2004-10-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEONG MEIKEI ,  REZNICEK ALEXANDER ,  YANG MIN

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a hybrid substrate, equipped with semiconductor layers, having different crystal orientations isolated by a conductive or an insulating interface.
SOLUTION: A method of providing a hybrid substrate, equipped with semiconductor layers having different crystal orientations that are isolated by a conductive or an insulating interface formed by employing semiconductor-to-semiconductor direct wafer bonding, is disclosed. The hybrid substrate may also be yielded by a method, employing a direct bonding method which provides an integrated semiconductor structure, in which various CMOSs are constructed on plane directions which enhance the performance of a device.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供配备有通过导电或绝缘界面隔离的不同晶体取向的半导体层的混合基板。 解决方案：提供一种提供混合基板的方法，该混合基板配备有通过采用半导体至半导体直接晶片接合形成的导电或绝缘界面隔离的具有不同晶体取向的半导体层。 也可以通过使用提供集成半导体结构的直接接合方法的方法来产生混合衬底，其中在平面方向上构造各种CMOS，这增强了器件的性能。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005109498A

公开(公告)日：2005-04-21

申请号：JP2004282572

申请日：2004-09-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAN VICTOR ,  GUARINI KATHRYN W ,  LEONG MEIKEI

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/336 ,  H01L21/68 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/00 ,  H01L27/06 ,  H01L27/085 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/6835 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68368 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a 3D (3-dimensional) integrating method of manufacturing 3D integrated circuit, in which a pFET is arranged on a crystal surface optimal for this device, and an nFET can be arranged on a crystal surface optimal for this type of device.
SOLUTION: In a first 3D integrating method, a first semiconductor device is constituted on a semiconductor surface of a first SOI (silicon-on-insulator) substrate, in advance, and a second semiconductor device is constituted on a semiconductor surface of a second SOI substrate in advance. After these two structures have been constituted in advance, these structures are combined mutually, and they are interconnected via a wafer, namely, via a penetration via hole. In a second 3D integrating method, the first semiconductor device is formed, in such a way that a blanket SOI substrate having a first SOI layer of a first crystal orientation is combined at a surface of the wafer, which has been manufactured, in advance and has the second semiconductor device, on a second SOI layer having a crystal orientation different from that of the first SOI layer and the first semiconductor device on the first SOI layer.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造3D集成电路的3D（3维）积分方法，其中pFET布置在该器件最佳的晶体表面上，并且nFET可以布置在晶体表面上 最适合这种类型的设备。 解决方案：在第一3D积分方法中，第一半导体器件预先在第一SOI（绝缘体上硅）衬底的半导体表面上构成，并且第二半导体器件构成在半导体表面上 第二SOI衬底。 在预先构成这两个结构之后，这些结构相互组合，并且它们通过晶片，即经由穿透通孔相互连接。 在第二3D积分方法中，第一半导体器件被形成为使得具有第一晶体取向的第一SOI层的覆盖SOI衬底预先在已经制造的晶片的表面上组合，并且 具有第二SOI层，具有不同于第一SOI层的晶体取向和第一SOI层上的第一半导体器件的第二SOI层。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2007142392A

公开(公告)日：2007-06-07

申请号：JP2006294972

申请日：2006-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEONG MEIKEI ,  LUDWIG THOMAS ,  EDWARD J NOWAKU ,  OUYANG QIQING C

IPC: H01L29/786 ,  H01L21/302 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66818 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a semiconductor structure including a plurality of fin FET devices.
SOLUTION: This invention concretely provides the method for forming the semiconductor structure including a plurality of fin FET devices, and provides a method for using a mask getting across it together with a chemical oxide removing (COR) process when a rectangular pattern is formed to demarcate a relatively fine fin. This method further includes a step for uniting the adjacent fins together by selectively using a material comprising a silicon. This invention is further related to the semiconductor structure formed by using this method.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种形成包括多个鳍式FET器件的半导体结构的方法。 解决方案：本发明具体地提供了形成包括多个鳍式FET器件的半导体结构的方法，并提供了当矩形图案是矩形图案时，使用与化学氧化物去除（COR）工艺一起穿过的掩模的方法 形成了划定相对较细的鳍。 该方法还包括通过选择性地使用包含硅的材料将相邻翅片结合在一起的步骤。 本发明还涉及通过使用该方法形成的半导体结构。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005175481A

公开(公告)日：2005-06-30

申请号：JP2004353555

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ZHANG YING ,  DORIS BRUCE B ,  KANARSKY THOMAS SAFRON ,  LEONG MEIKEI ,  KEDZIERSKI JAKUB TADEUSZ

IPC: H01L29/812 ,  H01L21/335 ,  H01L21/336 ,  H01L21/338 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To manufacture a high performance processor by achieving device width control in a FinFET device so as to provide a field effect device which performs high current drive in a given layout area.
SOLUTION: A field effect device, which has a body made of a crystalline semiconductor material and comprises at least one vertically oriented unit 11 and at least one horizontally oriented unit 12, is produced in an SOI layer through several etching steps. By providing a gate electrode 50, the segmented (unit type) field effect device can combine a FinFET type device, or a fully depleted silicon-on-insulator FET type device, and a fully depleted planar device.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过在FinFET器件中实现器件宽度控制来制造高性能处理器，以便提供在给定布局区域中执行高电流驱动的场效应器件。 解决方案：具有由晶体半导体材料制成的主体并且包括至少一个垂直取向单元11和至少一个水平取向单元12的场效应器件通过几个蚀刻步骤在SOI层中产生。 通过提供栅电极50，分段（单元型）场效应器件可以组合FinFET型器件或完全耗尽的绝缘体上硅FET器件和完全耗尽的平面器件。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005057284A

公开(公告)日：2005-03-03

申请号：JP2004223211

申请日：2004-07-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GUARINI KATHRYN W ,  LEONG MEIKEI ,  SHI LEATHEN ,  YANG MIN

IPC: H01L27/12 ,  H01L21/335 ,  H01L21/762 ,  H01L27/08

CPC classification number: H01L21/76275 ,  H01L21/76267 ,  H01L21/76283

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit device which is formed on a SOI(silicon-on-insulator) substrate, which can realize highest performance of a specific device and has different crystal orientations.
SOLUTION: The integrated circuit device includes at least the SOI substrate which has an upper semiconductor layer of a first crystal orientation and a semiconductor material of a second crystal orientation, the semiconductor material is substantially on the same plane surface and its thickness is the same to that of the upper semiconductor layer, and in an integrated circuit structure, the first crystal orientation is different from the second crystal orientation. The SOI substrate is formed by wafer bonding, ion implantation, and annealing.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种形成在SOI（绝缘体上硅）衬底上的集成电路器件，其能够实现特定器件的最高性能并具有不同的晶体取向。 解决方案：集成电路器件至少包括具有第一晶体取向的上半导体层和第二晶体取向的半导体材料的SOI衬底，半导体材料基本上在同一平面上，其厚度为 与上半导体层相同，在集成电路结构中，第一晶体取向与第二晶体取向不同。 SOI衬底通过晶片接合，离子注入和退火形成。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006057645A3

公开(公告)日：2006-11-30

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

公开(公告)号：WO2006057645A9

公开(公告)日：2006-09-14

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.