公开(公告)号：US3653066A

公开(公告)日：1972-03-28

申请号：US3653066D

申请日：1969-12-29

Applicant: IBM

Inventor： ROYSE DAVID ,  MACHOL GUENTHER K

IPC: G06K1/12 ,  G07F7/08 ,  G11B5/16 ,  G01D15/12

CPC classification number: G07F7/08 ,  G06K1/125 ,  G07F7/0833

Abstract: A terminal is provided for recording fixed and variable transaction data in both human and machine readable form from a credit card having an encoded magnetic stripe or track and embossed identification data and from settable means having an encoded magnetic portion and an embossed portion for keying in the variable transaction data. The magnetic copy stripe or track on a record form is held in contact with the magnetic stripe on the credit card and the encoded portions of the settable means. The remainder of the form is placed over the embossures on the settable means and on the credit card. A transfer magnet head and a pressure roller are moved along the form to transfer the magnetic information to the magnetic stripe on the record form and to imprint the embossed information on the remainder of the record form. The transfer encoded ticket thus prepared is compatible with a direct recorded ticket.

Abstract translation: 提供了一种终端，用于以具有编码的磁条或轨迹和压花识别数据的信用卡从人机和机器可读形式记录固定和可变交易数据，并且具有编码磁性部分和压印部分的可设置装置，用于键入 可变交易数据。 记录表格上的磁性复制条纹或轨迹与信用卡上的磁条和可设置装置的编码部分保持接触。 表格的其余部分放置在可设置装置和信用卡上的压花上。 转移磁头和压力辊沿着形式移动，以将磁信息传送到记录表格上的磁条，并将压印的信息压印在记录形式的其余部分上。 这样准备的传送编码票据与直接记录的票证兼容。

公开(公告)号：US3047853A

公开(公告)日：1962-07-31

申请号：US72647958

申请日：1958-04-04

Applicant: IBM

Inventor： MACHOL GUENTHER K

IPC: G11B20/14

CPC classification number: G11B20/1419

公开(公告)号：CA1066440A

公开(公告)日：1979-11-13

申请号：CA253068

申请日：1976-05-21

Applicant: IBM

Inventor： BOWMAN ROBERT A ,  MACHOL GUENTHER K ,  TERLET RENE H

IPC: H04J6/02

Abstract: TIME DIVISION MULTIPLEXED LOOP COMMUNICATION SYSTEM WITH DYNAMIC ALLOCATION OF CHANNELS In a time division multiplexed loop communication system, a plurality of terminals share one or more channels of a multichannel frame, with a second plurality of terminals assigned to different channels. The communications controller may dedicate one or more of the channels to one of the terminals automatically and dynamically. Alternatively, one of a plurality of terminals assigned to a particular channel group can interrupt the controller and become automatically selected for communication.

公开(公告)号：CA1119307A

公开(公告)日：1982-03-02

申请号：CA337635

申请日：1979-10-15

Applicant: IBM

Inventor： MACHOL GUENTHER K

IPC: G06F7/00 ,  G06F7/57 ,  G06F9/305 ,  G06F9/308 ,  G06F15/78 ,  G06F9/22

Abstract: MICROCOMPUTER HAVING SEPARATE BIT AND WORD ACCUMULATORS AND SEPARATE BIT AND WORD INSTRUCTION SETS A microprocessor chip architecture provides separate bit and word arithmetic and logic unit (ALU) and accumulator sets for processing data and executing instructions on either a bit or word basis. Separate instruction sets are provided for bit and word processing. The single bit instruction set is executed by the single bit ALU-accumulator set for serial operations and these instructions are designed to facilitate I/O operations. The word instruction set is executed by the word ALU-accumulator set for parallel operations and these instructions are designed to facilitate data transfer and manipulation. The address space includes a region which may be addressed on both a bit and word basis, thereby enabling the same data to be processed either as bits or words in order to optimize the current operation. Each bit of the word accumulator is addressable by the bit instructions, thereby eliminating the need for mask operations. An example is described in the use of both bit and word processing facilities to execute a double frequency (F/2F) data separation operation. SA977062

公开(公告)号：CA1137641A

公开(公告)日：1982-12-14

申请号：CA349769

申请日：1980-04-14

Applicant: IBM

Inventor： HOMAN MERLE E ,  MACHOL GUENTHER K ,  WARREN LARRY M

IPC: G06F9/30 ,  G06F12/06 ,  G06F15/78 ,  G06F9/24

Abstract: A microprocessor external instruction feature which provides for a single chip microprocessor with on-chip read only instruction store (ROS) that can also be operated with an off-chip instruction store. To accomplish this, the microprocessor instruction sequencing logic (instruction store, instruction register, instruction counter, and sequencing logic) is duplicated off-chip. An external instruction mode input pin signal causes the microprocessor to take its instructions from the external instruction store via 12 external instruction (XI) input pins instead of from the on-chip ROS. A branch decision output pin signal from the microprocessor, which indicates that the branch conditions have been met, causes the external instruction counter to be loaded with a branch address from the external instruction register instead of being stepped by external sequencing logic. A wait output pin signal causes the external instruction feature logic to suspend operations while the microprocessor is in its wait state. SA9-78-071

公开(公告)号：FR2311355A1

公开(公告)日：1976-12-10

申请号：FR7610913

申请日：1976-04-09

Applicant: IBM

Inventor： CROSS JON L ,  HOMAN MERLE E ,  MACHOL GUENTHER K ,  MALM RICHARD L ,  SVELUND LARRY E

IPC: G06F7/00 ,  G06F11/00 ,  G06F13/00 ,  G06F13/42 ,  H04B10/00 ,  G06F3/04

公开(公告)号：CA1066812A

公开(公告)日：1979-11-20

申请号：CA252273

申请日：1976-05-11

Applicant: IBM

Inventor： CROSS JON L ,  HOMAN MERLE E ,  MACHOL GUENTHER K ,  MALM RICHARD L ,  SVELUND LARRY E

IPC: G06F7/00 ,  G06F11/00 ,  G06F13/00 ,  G06F13/42 ,  H04B10/00 ,  G06F9/16

Abstract: APPARATUS FOR CONTROL AND DATA TRANSFER BETWEEN A SERIAL DATA TRANSMISSION MEDIUM AND A PLURALITY OF DEVICES Apparatus under microprocessor control for use in communicating over a serial communication loop with a remote attached control unit. It is capable of establishing frame synchronization, interpreting commands, assembling data and transmitting bits on the loop. The apparatus also communicates with I/O devices over a demand/response interface. A microprocessor interface with the loop includes loop sync control which establishes bit synchronization and generates a restart pulse at bit receive time and bit send time. The execution of instructions by the microprocessor is stopped and the microprocessor enters a wait state when it has finished all previous work and is ready to receive a loop bit. When it is time to receive the loop bit the microprocessor is restarted in response to the restart pulse from the loop synchronization. or output operations to a device, the microprocessor loads the device address and a device command or data into shift registers and initiates the transfer by setting a latch. When the transfer to the device is completed, this latch is reset in response to a signal from the device.

公开(公告)号：FR2311462A1

公开(公告)日：1976-12-10

申请号：FR7610166

申请日：1976-04-01

Applicant: IBM

Inventor： BOWMAN ROBERT A ,  MACHOL GUENTHER K ,  TERLET RENE H

IPC: H04L5/22 ,  G06F13/00 ,  H04L12/423 ,  H04M9/02

Abstract: In a time division multiplexed loop communication system, a plurality of terminals share one or more channels of a multichannel frame, with a second plurality of terminals assigned to different channels. The communications controller may dedicate one or more of the channels to one of the terminals automatically and dynamically. Alternatively, one of a plurality of terminals assigned to a particular channel group can interrupt the controller and become automatically selected for communication.